Commit Graph

28571 Commits

Author SHA1 Message Date
Julius Werner b55df4f1a8 rockchip/rk3399: Remove obsolete BL31 resource reservation
RK3399 SoC code still manually excludes the BL31 region from the memory
map, even though that is now automatically done with the BL31()
memlayout region. CB:31123 and CB:31538 just forgot to remove this line.
The resulting memory map stays the same.

Change-Id: I87458fa09f437b038af10e0fd9d76ef6d9394bc5
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31914
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ting Shen <phoenixshen@google.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-03-19 21:40:15 +00:00
Thomas Heijligen b0158e0b14 mb/intel/coffeelake_rvp: remove double selection in Kconfig
Change-Id: I0e1a66b3d1d7bd4633ad1df597f62ddbd38f46d4
Signed-off-by: Thomas Heijligen <thomas.heijligen@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31958
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2019-03-19 21:37:52 +00:00
Frans Hendriks b55cd54d1b soc/intel/braswell: Use IRQ 9 for SCI
Default reserved value of used for SCI IRQ.
Configure SCIS field to use IRQ 9.

BUG=N/A
TEST=Facebook FBG-1701 booting Embedded Linux

Change-Id: I09aca433528b6f64ad3ff3753ae8392c0d89cdc0
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31785
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
2019-03-19 21:37:37 +00:00
Maxim Polyakov 1217af5e1a mainboard: Add ASRock H110M-DVS
This board is compatible with Intel Skylake and Kaby Lake generation
processors. This patch contains the minimum configuration for booting
and stable operation of the Ubuntu OS (18.04.1, Linux kernel 4.15).
It is based on Intel RVP8 mainboard.

Intel Kaby Lake FSP 3.6.0 is used to initialize CPU and PCH.
Graphics init with libgfxinit.

Works:
  - Integrated graphics (only DVI port, tested with 1920x1080);
  - PEG x16 (FSP must be configured with BCT to enable PEG);
  - all PCIe x1 slots;
  - all USB and SATA ports;
  - SuperIO COM port for console;
  - onboard audio.

TODO:
  - other SuperIO functions;
  - onboard network chip;
  - suspend and resume;
  - documentation.

Tested on Intel Core i5-6600 processor with Seabios (rel-1.12.0-10-
g171fc89) and Tianocore/edk2 (vUDK2018-8-ge6eccfc) as a payload.

Change-Id: I69396edc50948cf1d0da649241ce92171d32daf7
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31603
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-03-19 21:36:49 +00:00
Elyes HAOUAS 03c60a5054 soc/intel/braswell/romstage: Drop unused 'include <rtc.h>'
Change-Id: I6577d9a31da44be5b57bb10497d9bd02fc9bbcd3
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31946
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-03-19 17:18:26 +00:00
Elyes HAOUAS 28b38cd365 src: Drop unused 'include <cbfs.h>'
Change-Id: If5c5ebacd103d7e1f09585cc4c52753b11ce84d0
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31953
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-03-19 17:14:39 +00:00
Subrata Banik b1434fce01 Fix 'unsigned int' to bare use of 'unsigned'
Change-Id: Iee09b601045d7785a0977a4f7ed7385b1d311044
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31913
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-03-19 04:45:58 +00:00
Shelley Chen d0e218384f mb/google/hatch: Set hatch to use SOC_INTEL_COMETLAKE
Move these configs to Kconfig.name as well.

BUG=b:127310803
BRANCH=None
TEST=emerge-hatch coreboot chromeos-bootimage

Change-Id: I793363740fa0730a1e9e1aa7a9fa82d2789334b4
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31852
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2019-03-18 21:07:54 +00:00
Nitheesh Sekar 717050d1d2 qcs405: Add DRAM resources
TEST=build

Change-Id: Iea79a942c297400c88aa205da713bcfcb8c51185
Signed-off-by: Sricharan R <sricharan@codeaurora.org>
Signed-off-by: Nitheesh Sekar <nsekar@codeaurora.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/29954
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-03-18 18:18:52 +00:00
Nitheesh Sekar ef75cca0e1 libpayload: qcs405: Add new Configs
Add Additional configs to enable Timer and CHROMEOS build.

TEST=build

Change-Id: I15273fdacab0a23e05e821c433cf939be35fab97
Signed-off-by: Sricharan R <sricharan@codeaurora.org>
Signed-off-by: Nitheesh Sekar <nsekar@codeaurora.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/29953
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-03-18 18:18:42 +00:00
Nitheesh Sekar 4da8d8d7fe qcs405: Add Timer support
Init frequency to 19.2 MHz

TEST=build

Change-Id: I566c7ff2b7085c9dd89ea74a08f3ba862feab2ab
Signed-off-by: Sricharan R <sricharan@codeaurora.org>
Signed-off-by: Nitheesh Sekar <nsekar@codeaurora.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/29952
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-03-18 18:18:28 +00:00
Nitheesh Sekar 6bee0cee20 soc/qualcomm/qcs405: Add MMU support
Initialize 1st 4GB as Device Memory, except:
 * 1st page: NULL address
 * System_IMEM: Cached SRAM
 * Boot_IMEM: Cached SRAM

Change-Id: I8c6353be2c0379ec94f91223805762a2286de06d
Signed-off-by: Sricharan R <sricharan@codeaurora.org>
Signed-off-by: Nitheesh Sekar <nsekar@codeaurora.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/29950
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-03-18 18:18:00 +00:00
Nitheesh Sekar 918fc00fb4 mainboard/google/mistral: Add support for Mistral
Adding a new board variant 'Mistral' based on qcs405 soc.

TEST=build

Change-Id: I7ecfad68bb50f42acf36f51bc3433add56597c3d
Signed-off-by: Sricharan R <sricharan@codeaurora.org>
Signed-off-by: Nitheesh Sekar <nsekar@codeaurora.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/29949
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-03-18 18:17:12 +00:00
Nitheesh Sekar 20e75878a8 soc/qualcomm/qcs405: Support for new SoC
Adding the basic infrastruture soc support for qcs405 and
a new build variant.

TEST=build

Change-Id: Ia379cf375e4459ed55cc36cb8a0a92cab18b705e
Signed-off-by: Sricharan R <sricharan@codeaurora.org>
Signed-off-by: Nitheesh Sekar <nsekar@codeaurora.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/29948
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-03-18 18:16:27 +00:00
Frans Hendriks ad5e0a8e65 soc/intel/braswell: Reserve IOAPIC and ROM resources
The mmio resouces IOAPIC and ROM area not reserved.
Reserve IOAPIC and ROM resources.

BUG=N/A
TEST=Intel CherryHill CRB booting Embedded Linux

Change-Id: I917c30892b46ac1d964e7bab339082d17a1e706d
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/29423
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-03-18 16:18:45 +00:00
Kyösti Mälkki bd74aaf534 mb/foxconn/g41m: Fix overridetree
The .chip_info field of PNP devices in overridetree
incorrectly pointed to southbridge config structure
in generated static.c files.

Change-Id: If507c8ea9c865ff86e127226b93a8579bcf39d8d
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31935
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-03-18 13:45:34 +00:00
Elyes HAOUAS ade13f03e1 src: Drop unused 'include <romstage_handoff.h>'
Change-Id: I311269967949533264e44fd3bb29ad3a06056653
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31941
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2019-03-18 12:05:59 +00:00
Angel Pons 22add8ea30 util/autoport: Rewrite readme.md
The last part of the file has not been modified much.

Change-Id: Icc45824d5d1298146f459d75f0a5121dbdd70d41
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/30969
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-03-18 09:22:06 +00:00
Angel Pons 08caa792e6 util/autoport: Trim gfx.did to size
Since the values are hardcoded, we might as well hardcode values that
make sense.

Change-Id: I3ac0e2d74a42c1fe55b1cdc3e2a970ae80cc9f37
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/30963
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-03-18 09:20:05 +00:00
Angel Pons 9b1ae44b28 util/autoport: fix default headers
Change-Id: I1b46d76a86f5db02ebc452d43472b51f0414ad96
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31927
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2019-03-18 09:19:30 +00:00
Maulik V Vaghela bfe4a59bc9 soc/intel/cannonlake: Pass coreboot debug interface info to FSP
coreboot have an option to use legacy UART or LPSS UART. FSP will use the
UART initialized by coreboot and we can choose an option to skip Uart
initialization by FSP.
For this, we need to pass correct debug interface flag to FSP through
which FSP will know which UART port to use. If we don't pass correct
interface information, FSP may try to dump logs on that port and it may
slow down the system.

BUG=none
BRANCH=none
TEST=Compile and boot with coreboot. Check FSP and coreboot logs are
coming on serial port.

Change-Id: I1ebb20c93e2c15ec085538509099de72bc9dd62c
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31884
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-03-18 09:18:18 +00:00
Patrick Rudolph 0f681dc5e6 include/cpu/x86/pae.h: Add missing include
Add the include for size_t.
Fixes compilation error on source files that do not include it.

Change-Id: Ic752886d94db18de89b8b8a5e70cf03965aeb5c3
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31922
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-03-18 09:17:19 +00:00
Joel Kitching 51ffa7e810 vboot: move assert in vboot_migrate_cbmem
Fix a potential null pointer dereference when calling
memcpy.  assert should be before the memcpy call,
and not after.

BUG=b:124141368, b:124192753
TEST=util/lint/checkpatch.pl -g origin/master..HEAD
TEST=util/abuild/abuild -B -e -y -c 50 -p none -x
TEST=make clean && make test-abuild
BRANCH=none

Change-Id: I5a2a99e906b9aa3bb33e1564d8d33a0aca7d06ac
Signed-off-by: Joel Kitching <kitching@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31923
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-03-18 09:17:01 +00:00
Elyes HAOUAS d2894f690a src/nsc/common/nsc.h: Drop unused include
Change-Id: Id3501e65a9d0c0b5ad98679f5e78f985e87cbe55
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31925
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2019-03-18 09:16:14 +00:00
Elyes HAOUAS d889508f16 mb/(ICH7): Remove initialization already done at early_init.c
V1CAP is a write-once register, and it is already programmed in
intel/i945/early_init.c.
Tested on 945G-M4 board (i945G + 82801GB).

Change-Id: I4469cb7505d584f10c98aec579a2d78bf1950bf3
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31004
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-03-18 09:15:59 +00:00
Elyes HAOUAS 3449fafec3 nb/intel/i945: Remove 2nd write on SLOTCAP (R/WO)
SLOTCAP is R/WO, it becomes RO after the first write.
Write already done on line #583.

Tested using kprint before and after on 945G-M4 board.

Change-Id: I27579bc634e357490defabb041457aaa010fb1c8
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31036
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-03-18 09:15:08 +00:00
Duncan Laurie 19a37d6420 ec/google/wilco: Enable software sync for VBOOT
Enable software sync by default if VBOOT is enabled.
The slow update option is also needed, but this is moving
to depthcharge so it is not defined here.

Change-Id: I046661fae7315f84e96293532b4e1568558df962
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31920
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-03-18 09:14:43 +00:00
Duncan Laurie a436877573 ec/google/wilco: Fix handling of commands that do not respond
If the command does not respond the driver should not wait for
it to complete before returning.

Tested with SMI debug enabled to ensure that the final command
does not report a failure.

Change-Id: I7c1bfa19a92e8332ac1aa6ff95f94ff4cbdf789d
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31919
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-03-18 09:14:36 +00:00
Duncan Laurie af39c82a36 soc/intel/common: Update ESPI disable option
Update the Kconfig option for disabling ESPI SMI source
to disable it entirely, not just when ACPI mode is disabled.

For the situations where this is needed (just the sarien
board) it is better to completely stop the EC from sending
any SMI events as no actions are taken.

Change-Id: Id94481bb2f0cfc948f350be45d360bfe40ddf018
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31918
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-03-18 09:14:25 +00:00
Lijian Zhao c563cf3030 mb/google/sarien: Enable BT Rkfill
Add bluetooth Rfkill function to recover the Bluetooth controller in
cases where itself has entered a bad state and needs to be recovered.

Bug=b:123342945
TEST=Boot up into OS and dump SSDT table, check there's _DSD entry under
Bluetooth devices with GPIO in.

Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Change-Id: Ibbe67887227af42b6c040deade7bf5da4ce3227f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31765
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-03-18 09:13:40 +00:00
Xiang Wang 313d53f6d3 src/mb/sifive/hifive-unleashed: initialize Gigabit Ethernet Controller
Initialize the clock of the Gigabit Ethernet Controller.

Change-Id: I172dc518c9b48c122289bba5a65beece925410d4
Signed-off-by: Xiang Wang <wxjstz@126.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31059
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Hug <philipp@hug.cx>
2019-03-18 09:12:46 +00:00
Martin Roth 09abb879a4 mainboard/google/kahlee: Don't use AMD's secure OS
Disable the use of AMD's Secure OS through the Kconfig option.

BUG=chromium:903833
TEST=Build google/aleena, verify types 02, 0c, 0d are removed
from PSP directory table

Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: Iabb0632eef88170dde45dea2e2e15b54b3a06f7b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31890
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
2019-03-18 09:12:10 +00:00
Marshall Dawson 25eb2bceb8 soc/amd/stoneyridge: Correct PSP SecureOs Kconfig symbol
Fix a spelling error in the name.

TEST=Build google/aleena and compare amdfw.rom before/after

Change-Id: I727ba1d6a8991caa1cdddcfca94c55c73954320a
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31904
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-03-18 09:11:54 +00:00
Subrata Banik 2b4ba5105c mb/intel/../../cml_u: Override LPSS related FSP UPD for CMLRVP
This patch overrides required LPSS FSP UPDs for CMLRVP from devicetree.cb
File devicetree-override.cb will override required UPDs and is only
applicable to CML soc for now

Change-Id: I82e3323df952762e2d9c14f1e3cfa75872ccc9b4
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31285
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-03-18 06:20:59 +00:00
Subrata Banik 695f7249a4 mb/intel/coffeelake_rvp: Add cml_u board support
This patch adds support to select CMLRVP board.

Change-Id: I5f81b47f33345edefa0a7064559d9531e1d20eff
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31283
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-03-18 06:20:34 +00:00
Subrata Banik 1a27b0bc38 mb/intel/coffeelake_rvp/../cml_u: Do initial mainboard commit
Clone entirely from mainboard/intel/coffeelake_rvp/../whl_u
commit id: 73916defba

Change-Id: Icc32a6e1940ba2d13f3ad74cddbb4b75a637cc18
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31281
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-03-18 06:20:14 +00:00
Subrata Banik 217ca36377 resources: introduce io_resource()
This patch creates new resource function to perform allocation
of IO resource, similar to mmio_resource() function does for MMIO.

Change-Id: I3fdcabb14302537d6074bfd6a362690c06b66bb5
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31911
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
2019-03-17 03:45:50 +00:00
Subrata Banik 41483c9dff soc/intel/cannonlake: Add required FSP UPD changes for CML
This patch adds required FSP UPD changes for CometLake SoC.
Also this patch tries to create common parse logic for CometLake as
well as cannonlake SOC.

We parse device tree parameters for PCI devices and fill values in FSP
UPDs. We fill UPDs based on pci device config as well as SerialIoDev
config of devicetree.
For PCI devices, if PCI device is disabled from devicetree, we'll assign
disable value to FSP UPD.
In case devicetree doesn't fill this parameter or value is invalid in
SerialIoDev config, default mode will be set to PCI.
In case of valid value, we'll fill the same value into FSP UPD.

BUG=none
BRANCH=none
TEST=check if CML board boots and proper UPD values are filled.

Change-Id: Ib92b660409ab01d70358042b2ed29b8bf9cab26d
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31284
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: V Sowmya <v.sowmya@intel.com>
2019-03-16 22:48:06 +00:00
Nico Huber ebd8a4f90c x86/smbios: Untangle system and board tables
We were used to set the same values in the system and board tables.
We'll keep the mainboard values as defaults for the system tables,
so nothing changes unless somebody overrides the system table hooks.

Change-Id: I3c9c95a1307529c3137647a161a698a4c3daa0ae
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/29477
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2019-03-16 16:22:16 +00:00
Kyösti Mälkki 4663f45caa device/pci_ops: Have only default PCI bus ops available
In the current state of the tree we do not utilise the
mechanism of having per-device overrides for PCI bus
ops.

This change effectively inlines all PCI config accessors
for ramstage as well.

Change-Id: I11c37cadfcbef8fb5657dec6d620e6bccab311a4
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31753
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2019-03-16 15:19:33 +00:00
Kyösti Mälkki 34cf5619f9 device/pci_ops: Reuse romstage PCI config for ramstage
By changing the signatures we do not need to define
PCI config accessors separately for ramstage.

Change-Id: I9364cb34fe8127972c772516a0a0b1d281c5ed00
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31685
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-03-16 15:19:06 +00:00
Elyes HAOUAS 74aa99a543 src: Drop unused '#include <halt.h>'
Change-Id: Ie7afe77053a21bcf6a1bf314570f897d1791a620
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31921
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-03-16 11:46:58 +00:00
Elyes HAOUAS 4b7202e250 src: Drop unused 'include <device/pciexp.h>'
Change-Id: I9b4d72116a66d5a256659fa82682497ef3481e77
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31924
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-03-16 11:46:38 +00:00
Patrick Rudolph 5926ae24a6 drivers/intel/fsp1_0: Deduplicate code
Move ChipsetFspReturnPoint() to drivers/intel/fsp1_0.

Allows to have a common entry after FSP-M.

Change-Id: I064ae67041c521ee92877cff30c814fce7b08e1f
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31713
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: David Guckian
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com>
2019-03-16 09:01:50 +00:00
Julius Werner 0e3f7d4780 Revert "lint/clang-format: set to 96 chars per line"
This reverts commit 626ba097a2.

This change was submitted under the incorrect assumption that there was
agreement on a coding style change. There wasn't, so while the issue is
under discussion we should revert to the previous status quo.

Making clang-format honor the line length is a separate issue from
changing the line length, and can be reuploaded as a separate CL.

Change-Id: I433c82c95a897b3113cace3668cc8ce0f1ab75bf
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31916
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-03-15 23:05:06 +00:00
Julius Werner ada45a3148 Revert "Documentation: Our coding style now allows 80 + 2*8 columns in a line"
This reverts commit b3a8cc54db.

This change was submitted under the incorrect assumption that there was
agreement on a coding style change. There wasn't, so while the issue is
under discussion we should revert to the previous status quo.

Change-Id: I37a5585764346af11a98bdf58c810dd3cf5bfe40
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31915
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-03-15 23:04:56 +00:00
Joel Kitching 2c8243cf6d drivers/intel/fsp2_0: fix TPM setup and MRC cache hash logic
When VBOOT_STARTS_IN_BOOTBLOCK is selected, the tpm_setup call
in memory_init.c is not used.

When VBOOT_STARTS_IN_ROMSTAGE is selected, the tpm_setup call
in memory_init.c is triggered.  However, when verstage runs,
tpm_setup is called yet again, and an error is triggered from
the multiple initialization calls.

Since there are currently no boards using
VBOOT_STARTS_IN_ROMSTAGE + FSP2_0_USES_TPM_MRC_HASH, disable
this combination via Kconfig, and remove the tpm_setup call
from Intel FSP memory initializion code.

* VBOOT=y VBOOT_STARTS_IN_BOOTBLOCK=y
  vboot is enabled, and TPM is setup prior to Intel FSP memory
  initialization.  Allow FSP2_0_USES_TPM_MRC_HASH option.

* VBOOT=y VBOOT_STARTS_IN_BOOTBLOCK=n
  vboot is enabled, but TPM is setup in romstage, after Intel
  FSP memory initialization.  Disallow FSP2_0_USES_TPM_MRC_HASH
  option.

* VBOOT=n
  vboot is disabled.  Disallow FSP2_0_USES_TPM_MRC_HASH option.

See bug for more information:
https://bugs.chromium.org/p/chromium/issues/detail?id=940377

BUG=chromium:940377
TEST=util/lint/checkpatch.pl -g origin/master..HEAD
TEST=util/abuild/abuild -B -e -y -c 50 -p none -x
TEST=make clean && make test-abuild
BRANCH=none

Change-Id: I4ba91c275c33245be61041cb592e52f861dbafe6
Signed-off-by: Joel Kitching <kitching@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31837
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-03-15 20:23:03 +00:00
Furquan Shaikh 6e401cf7e6 soc/intel/cannonlake: Fix GEN_PMCON bit checks
CNL PCH has PWR_FLR, SUS_PWR_FLR and HOST_RST_STS bits in GEN_PMCON_A
and so this change updates the check for these bits to use GEN_PMCON_A
instead of GEN_PMCON_B.

BUG=b:128482282
TEST=Verified that prev_sleep_state is reported correctly when booting
from S5.

Change-Id: I75780a004ded8f282ffb3feb0cdc76233ebfd4f2
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31908
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-03-15 19:52:30 +00:00
Duncan Laurie 90a96c77a9 ec/google/wilco: Clear S0ix support bit at boot
To ensure the power button functions as expected in firmware ensure
that the EC is not in "S0ix supported OS" mode and expecting the
power button to be handled by the virtual button interface.

BUG=b:128409889
TEST=Verify that the power button works at the developer screen
when the system is rebooted from within Chrome OS.  Also ensure
that it works when external warm reset signal is asserted by H1.

Change-Id: Ic323515e3b8be08bac4f0f82e25f2f78c2f22833
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31903
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-03-15 15:31:59 +00:00
Jett Rink a29d866f1c ec/google/wilco: coalesce tent mode to tablet mode
Both tent mode (0x01) and tablet mode (0x02) should be considered tablet
mode by ChromeOS.

BRANCH=none
BUG=b:122052438
TEST=ChromeOS enters tablet mode when lid angle exceeds 180

Change-Id: I89ba8141350fc628c8cff89d5f33aa47c6ae6afe
Signed-off-by: Jett Rink <jettrink@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31907
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-03-15 13:12:52 +00:00