Commit Graph

22448 Commits

Author SHA1 Message Date
Kyösti Mälkki 91b682c33c soc/amd/stoneyridge: Move oem_fan_control()
While at it, replace LibAmdMemFill() with memset().

Change-Id: I770cab446add8f305f02e365e7c9763df88cd958
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/21192
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-08-25 04:20:36 +00:00
Martin Roth 0ff2e01e80 amd/pi/hudson: Move oem_fan_control()
It was not intentional to change oem_fan_control() to non-static
with commit
  23e5ba9 binarypi mainboards: Clean up IS_ENABLED fan control

Every platform except bettong had its own static version of
oem_fan_control, so remove the definition of oem_fan_control from imc.h,
and move it out of imc.c into bettong's BiosCallOuts.c.

Change-Id: Ie95ac1fd3a57259bb35796903aa8753ef0e70d70
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/21189
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-08-25 01:16:10 +00:00
Kyösti Mälkki d3af7d7fcc asrock/imb-a180: Remove commented oem_fan_control()
Change-Id: Ibfbb2ff2d9776fe91a8a09561d9c32eb49a56db6
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/21187
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2017-08-25 00:48:09 +00:00
Marc Jones 05b2f69cd0 amd/pi/hudson: Clean up makefile.inc
Sort makefile.inc into rom, ram, ver, smm stages and alphabetize.

Change-Id: Ic8c6ca2b57527fcc96c135cc801a098201bf0465
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/19640
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2017-08-24 17:07:30 +00:00
Pratik Prajapati 5f34b37d80 mainboard/intel/cannonlake_rvp: set Max CPUs and Mainboard Family
Set MAX_CPUS and MAINBOARD_FAMILY for cannonlake RVP.

Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com>

Change-Id: Ic6ef7e4f247ac2d227bab3b53512c659c5e72da7
Reviewed-on: https://review.coreboot.org/21152
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-08-24 16:23:29 +00:00
Pratik Prajapati 01eda28bff soc/intel/cannonlake: Add cpu.c and MP init support
Add initial MP init support. This boots up all CPUs.

Change-Id: Ia33691c17c663d704abf65320d4bf1262239524d
Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com>
Reviewed-on: https://review.coreboot.org/21081
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-08-24 16:06:30 +00:00
Marshall Dawson 23e5ba9a73 binarypi mainboards: Clean up IS_ENABLED fan control
Remove all checks for #if IS_ENABLED(CONFIG_HUDSON_IMC_FWM) around
the imc.h includes.  Convert from #if to if() for all fan control
setup code.  Where necessary, make functions non-static to match the
prototypes in imc.h.

Change-Id: If88af42d00227285931829441909a982fc292b2b
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/21058
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2017-08-24 11:48:38 +00:00
Marshall Dawson 6dd620bf10 AGESA mainboards: Clean up IS_ENABLED fan control
Remove all checks for #if IS_ENABLED(CONFIG_HUDSON_IMC_FWM) around
the imc.h includes.  Convert all #if to if() for fan control setup.

Change-Id: I04a9fbbf6f64f45e1a0b544267bfe840ce7fa1d9
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/21059
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2017-08-24 11:47:36 +00:00
Marshall Dawson 0bf3f55b5c amd/pi/hudson: Convert 48Mhz en to read/write32
Change-Id: I91e09757e5eea1eaf9b76921ad032ad2b79c14c5
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/21033
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2017-08-24 11:40:43 +00:00
Marshall Dawson 9e741bb218 amd/bettong: Fix IS_ENABLED for xHCI
Convert from #if to if().

Change-Id: Icf6db485735cb8bbadb3e742a079d0bafaacd79c
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/21060
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2017-08-24 11:33:44 +00:00
Marc Jones 08f7d1ae0d mainboard/via*: Drop AMD car.h file
Don't include src/include/cpu/amd/car.h in Via motherboards.

Change-Id: I9d2b3cfb619cf831c7a677992ca03d5f42e5ffd1
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/19404
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Martin Roth <martinroth@google.com>
2017-08-24 11:32:08 +00:00
Kyösti Mälkki 2900d4b92e AGESA: Sync f15tn and f15rl northbridge code
Change-Id: Ia55c82f2245335a5d02e4d6567f606596c8439c0
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/20772
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2017-08-24 10:53:01 +00:00
Kyösti Mälkki 74e854ca78 gizmosphere/gizmo2: Switch away from AGESA_LEGACY
Change-Id: Ief40319f5ff83c408e5a2b7f13572feabfab03a4
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/20723
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2017-08-24 10:37:14 +00:00
Kyösti Mälkki a7aa57a6ed biostar/am1ml: Switch away from AGESA_LEGACY
Change-Id: I11ce2a558fe12f8f163dbe3dc52952a273b813ee
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/20722
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2017-08-24 10:36:42 +00:00
Kyösti Mälkki f27cb243c2 hp/abm: Switch away from AGESA_LEGACY
Change-Id: Ie2f1eb5a101b9c392a7bd5cb2338dd6a6fdcfe52
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/20721
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2017-08-24 10:34:36 +00:00
Kyösti Mälkki ffdb6e87c8 hp/pavilion_m6_1035dx: Switch away from AGESA_LEGACY
Change-Id: Iffc176522e943c003e2625d8e15341b281a261eb
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/20720
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2017-08-24 10:32:09 +00:00
Kyösti Mälkki acc8ac649d amd/thatcher: Switch away from AGESA_LEGACY
Change-Id: I7194eb910cccc454c5f20c23629ff2a45b1a9079
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/20719
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2017-08-24 10:31:50 +00:00
Kyösti Mälkki 46379c74ad amd/parmer: Switch away from AGESA_LEGACY
Change-Id: I3730bf87030b7e20991e1de00d2024e4b02f4c19
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/20718
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2017-08-24 10:31:18 +00:00
Kyösti Mälkki 65200be7fe bap/ode_e20XX: Switch away from AGESA_LEGACY_WRAPPER
Change-Id: Ia747b3bc149a672a6de2ecf0308141172321a493
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/20717
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2017-08-24 10:31:06 +00:00
Kyösti Mälkki 6dcd4bcf77 amd/olivehill: Switch away from AGESA_LEGACY_WRAPPER
Change-Id: I646a8f4cfc1df8648a72e58814c36ea66b48e9d7
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/20715
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2017-08-24 10:30:51 +00:00
Kyösti Mälkki aeadd84e7b asrock/imb-a180: Switch away from AGESA_LEGACY_WRAPPER
Change-Id: I5e6e4cabe2b93c41da19412ec3ae2dfaa114bcc0
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/20714
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2017-08-24 10:30:28 +00:00
Kyösti Mälkki a84e34be25 msi/ms7721: Switch away from AGESA_LEGACY_WRAPPER
Change-Id: I39a0b4acbe44dca8be63201502be739d954c8a33
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/20713
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2017-08-24 10:30:18 +00:00
Kyösti Mälkki ffa527002a asus/f2a85-m: Switch away from AGESA_LEGACY_WRAPPER
Change-Id: I5a6373ac03d942cd16905c9e8360f7179b8eea61
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/20712
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2017-08-24 10:30:03 +00:00
Kyösti Mälkki 8176af91e8 amd/torpedo: Switch away from AGESA_LEGACY_WRAPPER
Change-Id: Iac0998a56b4e297c512fcba98d3dbb4253c9b526
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/20711
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2017-08-24 10:29:52 +00:00
Tim Chen 1f3af89895 mb/google/coral: Copy devicetree.cb from baseboard
It is a copy from baseboard/devicetree.cb  (coreboot.org ToT)

BUG=b:64880573
BRANCH=master
TEST=emerge-coral coreboot chromeos-bootimage

Change-Id: I5db730c1974a96547fe7fda63689b7c5bfaefc66
Signed-off-by: Tim Chen <Tim-Chen@quantatw.com>
Reviewed-on: https://review.coreboot.org/21130
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-08-24 03:19:11 +00:00
Subrata Banik f5fe3590af soc/intel/skylake: Usable dram top calculation based on HW registers
This patch ensures that entire system memory calculation is done
based on host bridge registers.

BRANCH=none
BUG=b:63974384
TEST=Build and boot eve and poppy successfully with below configurations
1. Booting to OS with no UPD change
2. Enable ProbelessTrace UPD and boot to OS.
3. Enable PRMRR with size 1MB and boot to OS.
4. Enable PRMRR with size 32MB and boot to OS.
5. Enable PRMRR with size 2MB and unable to boot to OS due to
unsupported PRMRR size.

Change-Id: I9966cc4f2caa70b9880056193d5a5631493c3f3d
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/21150
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-08-23 17:56:50 +00:00
Martin Roth 89942a5aa7 Update depthcharge stable to upstream master
Updating from commit id 5a086f5c - Tue Jul 11 23:57:30 2017:
(ps8751: enable software sync.)

to commit id a843f262 - Wed Aug 16 23:37:52 2017:
(kahlee: select emmc boot first if available)

This brings in 20 new commits.

This matches with the updated vboot submodule.

Change-Id: If030bc3e75dd470838590540880213bd841154b8
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/21075
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2017-08-23 16:33:05 +00:00
Martin Roth 66dce275e5 Update vboot submodule to upstream master
Updating from commit id 8b714252 - 2017-07-18 02:36:16
(crossystem: Remove defunct sw_wpsw_bootfield)

to commit id 8c4b8285 - 2017-08-14 20:37:45 -0700
(detachables: Skip "Enable Developer Mode" in DEV mode)

This brings in 6 new commits.

Change-Id: I7769035453796a162c6313cd0c87661ef1e64f89
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/21074
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2017-08-23 16:32:52 +00:00
Subrata Banik d3f0243299 soc/intel/common: Early system agent library access in postcar stage
BRANCH=none
BUG=b:63974384
TEST=Build and boot eve successfully.

Change-Id: Ie5558cdb7acacc34451e1cf63a3e4239e7901c67
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/21149
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-08-23 16:17:19 +00:00
Subrata Banik bd6ac22f48 soc/intel/common: Add functions into common system agent library
This patch to add helper functions for memory layout design
based on PCI Host Bridge/DRAM registers.

BRANCH=none
BUG=b:63974384
TEST=Build and boot eve successfully.

Change-Id: I95250ef493c9844b8c46528f1f7de8a42cba88a2
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/21133
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-08-23 16:17:04 +00:00
zhaojohn 53461ad1f8 src/mainboard/intel/cannonlake: Add gpio support for cannonlake
Add gpio pins configuration for cannonlake rvp u/y boards.

Change-Id: Ia077a070979401fe7bd23bda110d2b66a038d9fc
Signed-off-by: john zhao <john.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/21139
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-08-23 15:53:10 +00:00
Kane Chen 5bddcc48b8 soc/intel/apollolake: Allow overriding dev tree settings by board
This change provides interface to override dev tree settings per
board due to many projects share same devicetree.cb.

BUG=b:64880573
TEST=Verify that dev tree settings can be overridden in mainboard
     on coral

Change-Id: I349b1678d9e66022b586b6c7f344b831ed631c74
Signed-off-by: Kane Chen <kane.chen@intel.com>
Reviewed-on: https://review.coreboot.org/21142
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-08-23 15:52:48 +00:00
Bill XIE a0d31d8d7d mb/lenovo/t430s: Enable libgfxinit
Tested on T430s with an external screen connected to every one of the
DP ports (miniDP on mainboard, two DP ports on dock), the GRUB payload
can display on both the external screen and the internal LVDS screen.

This is a copy-paste of I8f270d55 "mb/lenovo/x230: Enable libgfxinit".

Change-Id: Ifb1471ecb18927c30c61c64011cbb0e20a465558
Signed-off-by: Bill XIE <persmule@gmail.com>
Reviewed-on: https://review.coreboot.org/21070
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2017-08-23 08:36:55 +00:00
Kyösti Mälkki 538a570c98 sb/via/k8t890: Define ACPI sleep states
Change-Id: I9afd5eaab5f8e897dea037f32e1666ad31b0f8df
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/21144
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2017-08-23 03:39:54 +00:00
Kyösti Mälkki bbd60e31be soc/amd/stoneyridge ACPI: Sync sleepstates.asl definitions
Sync file with southbridge/amd/common/sleepstates.asl.

SSFG was meant to be used as a mask to enable sleepstates
_S1 thru _S4. However as a logical instead of bitwise 'and'
operation was used, all the states were enabled if only
one was marked available.

Change-Id: I674953f1a5add74e16ddd84c252e8d21501ffefd
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/21092
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2017-08-23 03:39:06 +00:00
Kyösti Mälkki fb94585554 sb/amd/amd8111: Define ACPI sleep states
Note that against the specs, these definitions repeat
the sleep type also in the reserved fields 3 and 4.
For consistency, don't fix it here now.

Entry for \_S3 is now masked off if HAVE_ACPI_RESUME=n.

Change-Id: Icdc4c81d07fe7a99d5b0f8fa23e9443f58a40ab9
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/21143
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2017-08-23 03:36:15 +00:00
Kyösti Mälkki 714709fde6 AMD fam10 ACPI: Use common fixed sleepstates.asl
SSFG was meant to be used as a mask to enable sleepstates
_S1 thru _S4. However as a logical instead of bitwise 'and'
operation was used, all the states were enabled if only
one was marked available.

Note that all boards incorrectly had SSFG == 0x0D that previously
enabled ACPI S3 sleep state even when it was not available.

Change-Id: Ia948becff079383cbf861468da9e8a3ebbf213cb
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/21093
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2017-08-23 03:36:05 +00:00
Kyösti Mälkki 390ba044dc AGESA binaryPI: Consolidate and fix sleep states
SSFG was meant to be used as a mask to enable sleep states
_S1 thru _S4. However as a logical instead of bitwise 'and'
operation was used, all the states were enabled if only
one was marked available.

State _S3 is now set conditionally if HAVE_ACPI_RESUME=y.
For pi/hudson this had been fixed already preprocessor.

Note that all boards had SSFG == 0x0D that previously
enabled ACPI S3 sleep state even when it was not available.
States _S1 and _S2 still appear enabled in ASL/AML
but may not actually work.

TEST: 'cat /sys/power/state' and notice choice 'mem' was
removed from the list of available sleep states.

Change-Id: I27d616871c1771f0c87d8fba23d4ce1569607765
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/21091
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2017-08-23 03:35:58 +00:00
Kyösti Mälkki 1438245334 AMD K8 fam10-15: Tidy up CAR stack switch
Return to empty stack before making the switch.

Change-Id: I6d6f633933fac5bc08d9542c371715f737fb42cf
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/20574
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
2017-08-22 20:25:15 +00:00
Kyösti Mälkki 90e07b460c AMD K8 fam10-15: Consolidate post_cache_as_ram call
Change-Id: I5e7890aafbc8c80716ee49690e306482a482a863
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/20573
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
2017-08-22 20:24:38 +00:00
Kyösti Mälkki b98391c0ee AMD K8 fam10-15: Tidy up CAR disable
Avoid conflicting disable_cache_as_ram() declaration and tidy
up include for inlined function.

Change-Id: Iba77c711f5eb023566b7d8ba148583948661bc99
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/20563
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2017-08-22 20:24:31 +00:00
Mariusz Szafranski a429761b7b vendorcode/intel/fsp/fsp2_0/denverton_ns: Add FSP header files for Denverton_NS SoC
This change adds the FSP header files for FSP version 2.0 (15D50)
for the Intel Denverton_NS SoC.

Change-Id: I9672610df09089c549e74072345781bea0b4d06f
Signed-off-by: Mariusz Szafranski <mariuszx.szafranski@intel.com>
Reviewed-on: https://review.coreboot.org/20805
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: FEI WANG <wangfei.jimei@gmail.com>
Reviewed-by: Brenton Dong <brenton.m.dong@intel.com>
2017-08-22 19:11:23 +00:00
Pratik Prajapati 0f2f069b4f soc/intel/cannonlake: Define soc_intel_cannonlake_config
- Populate soc_intel_cannonlake_config
- Add usb.h and vr_config.h for CannonLake

Change-Id: I2a6e737594da1e766b157a38942e19a4f7fb9dfa
Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com>
Reviewed-on: https://review.coreboot.org/21080
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-08-22 18:01:39 +00:00
Patrick Georgi 4bd68b8e4f ec/google: Detect keyboard backlight at runtime
This enables adding the backlight driver to boards that may or may not
come with a keyboard backlight function.
It's the responsibility of the EC to report if that feature exists, but
that's not a big extra burden given that it already keeps track of
everything else related to the backlight.

BUG=b:64705535
BRANCH=none
CQ-DEPEND=CL:620595
TEST=configured KBLE manually and noticed the presence/absence of
/sys/devices/platform/GOOG0002:00/ on a Chrome OS Linux kernel,
corresponding to the value reported by the EC.

Change-Id: Idc36bfaa6e69581ba19b52d37af6956f63cfdb8f
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/21099
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-08-22 17:59:20 +00:00
Barnali Sarkar fbf1018805 soc/intel/skylake: Lock sideband access in coreboot and not in FSP
The Sideband Acces locking code is skipped from FSP by setting an
FSP-S UPD called PchSbAccessUnlock. This locking is being done in
coreboot during finalize.c.

This is done because coreboot was failing to disable HECI1 device
using Sideband interface during finalize.c if FSP already locks
the Sideband access mechanism before that.

So, as a solution, coreboot passes an UPD to skip the locking
in FSP, and in finalize.c, after disabling HECI, it removes the
Sideband access.

BUG=b:63877089
BRANCH=none
TEST=Build and boot poppy to check lspci not showing Intel ME
controller in the PCI device list.

Change-Id: I8dba4c97480200507969b0f2873337f97bd2ff6a
Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com>
Reviewed-on: https://review.coreboot.org/20956
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-08-22 17:35:38 +00:00
Akshu Agrawal f7cd2f5b94 google/kahlee: Enable ALS connected to EC
Kahlee has an ambient light sensor connected to the EC.

TEST=Can see the device in /sys/bus/iio
BUG=b:62030268

Change-Id: Id1138a0fc5270489a734bdf8b1f4ac02d358c0df
Signed-off-by: Akshu Agrawal <akshu.agrawal@amd.com>
Reviewed-on: https://review.coreboot.org/21146
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-08-22 17:21:33 +00:00
Pratik Prajapati ee9168737f mainboard/intel/cannonlake_rvp: remove redundant devicetree.cb
devicetree.cb of cannonlake-u and y variant gets picked up
from src/mainboard/intel/cannonlake_rvp/variants/cnl_[u/y]

Change-Id: I83f636c93407a6fe17114582506397c46d1b4e20
Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com>
Reviewed-on: https://review.coreboot.org/21137
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-08-22 17:18:51 +00:00
Pratik Prajapati 3c15a39ea1 mainboard/intel/cannonlake-y: populate PCI devices
Define and populate PCI devices in devicetree for CNL-Y RVP

Change-Id: I311437798274dd48b0898f0832bf03d86fd9d3a6
Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com>
Reviewed-on: https://review.coreboot.org/21055
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2017-08-22 14:51:59 +00:00
Pratik Prajapati 1785f8b2f5 mainboard/intel/cannonlake-u: populate PCI devices
Define and populate PCI devices in devicetree for CNL-U RVP

Change-Id: Id04f5efe77a04c180b5dd392da777195bd9fb7a3
Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com>
Reviewed-on: https://review.coreboot.org/21054
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2017-08-22 14:51:55 +00:00
Harry Pan 4a2cef4ef7 mainboard/google/coral: Overwrite family code for coral models.
This patch assigns the code of coral family, such that,
the 'mosys platform family' returns 'Google_Coral'.

BUG=b:64467244, b:64501879
BRANCH=none
TEST=Examine 'mosys platform family' w/ new firmware.

Change-Id: I1d8f8ca2166a1d80855608cf5b64b0cc7bf3dc93
Signed-off-by: Harry Pan <harry.pan@intel.com>
Reviewed-on: https://review.coreboot.org/21136
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-08-22 14:51:27 +00:00