Commit Graph

30581 Commits

Author SHA1 Message Date
Angel Pons 6549661b9c nb/intel/pineview: Guard DMIBAR/EPBAR macro parameters
Add brackets around the parameters to avoid operation order problems.

Tested with BUILD_TIMELESS=1, Foxconn D41S remains identical.

Change-Id: I347466f56d3d5fb3793b3a25e4a825c844e50d42
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45386
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-09-17 19:59:59 +00:00
Angel Pons d25e2f6c80 nb/intel/pineview/iomap.h: Rename to memmap.h
It primarily contains definitions for MMIO windows.

Change-Id: I8cd639c8c7d400a5bfd73735113dd27dd6f948e6
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45385
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-09-17 19:59:48 +00:00
Angel Pons 298d34d8ff nb/intel/ironlake: Do not re-read ME UMA size
It has been read twice already, so don't read it a third time.

Change-Id: I56ec3a10246f6ebe8074e7b8c164bda6b90eee87
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45363
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-09-17 19:59:29 +00:00
Angel Pons 8690746efb nb/intel/ironlake: Drop some unused function parameters
Some of the HECI functions do not need raminfo at all.

Change-Id: If0720fa87e5e18820db77a1b61bcdb42ecc538fb
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45362
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-09-17 19:59:13 +00:00
Angel Pons d02f3303d9 nb/intel/ironlake: Drop `heci_bar` field from raminit
This field is only written to, never read. Drop it from raminfo.
Also, bump MRC_CACHE_VERSION as the saved data layout has changed.

Change-Id: I83d6e69addff996e2f18472d3e1d4f7b9ba974fd
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45361
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-09-17 19:59:04 +00:00
Angel Pons 122e4ebd7d nb/intel/haswell: Clean up register definitions
Several registers have been copy-pasted from i945 and do not exist on
Haswell. Moreover, other register definitions were missing. Although
most of them are unused, native platform init may eventually use them.

Tested with BUILD_TIMELESS=1, Asrock B85M Pro4 remains identical.

Change-Id: I6b3a47b2af406da6b030d417f14a2f4d394aa9c8
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45353
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-17 19:58:33 +00:00
Angel Pons e5ec50c236 nb/intel/haswell: Guard DMIBAR/EPBAR macro parameters
Add brackets around the parameters to avoid operation order problems.

Tested with BUILD_TIMELESS=1, Asrock B85M Pro4 remains identical.

Change-Id: I5e1a02ba2ebf468f0d80b7f1838766280b6b7b22
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45352
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-17 19:58:00 +00:00
Angel Pons a3cb322018 nb/intel/haswell: Introduce memmap.h
Move all memory map definitions into a separate header.

Tested with BUILD_TIMELESS=1, Asrock B85M Pro4 remains identical.

Change-Id: Ib275f9ad8ca9ff343604c9e8cbb130c74ddad54f
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45351
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-17 19:57:50 +00:00
Angel Pons 743159396a nb/intel/sandybridge: Drop `void *` cast in `MCHBAR32`
This changes the binary for the native raminit code path.

Tested on Asus P8Z77-V LX2, still boots with native raminit.

Change-Id: Ie8f1205a64e5264cb909d67c1dd402c18a6241ad
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45350
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-17 19:57:37 +00:00
Angel Pons c8027454ba nb/intel/sandybridge: Drop casts from DEFAULT_{MCHBAR,DMIBAR}
This allows us to drop some casts to uintptr_t around the tree.
The MCHBAR32 macro still needs a cast to preserve reproducibility.
Only the native raminit path needs the cast, the MRC path does not.

Tested with BUILD_TIMELESS=1, these boards remain identical:
 - Lenovo ThinkPad X230
 - Dell OptiPlex 9010
 - Roda RW11 (with MRC raminit)

Change-Id: I8ca1c35e2c1f1b4f0d83bd7bb080b8667dbe3cb3
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45349
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-17 19:35:19 +00:00
Angel Pons 92717ff3e4 nb/intel/sandybridge: Drop invalid `DEFAULT_RCBABASE` macro
RCBA is located in the PCH. Replace all instances with the
already-defined `DEFAULT_RCBA` macro, which is equivalent.

Change-Id: I4b92737820b126d32da09b69e09675464aa22e31
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45348
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-17 19:35:03 +00:00
Angel Pons 10240510a7 nb/intel/ironlake: Drop invalid `DEFAULT_RCBABASE` macro
This macro is unused, and RCBA is located in the PCH. Drop it.

Change-Id: Id7c095496360bbe96dc2a36dcc557a1481c02c31
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45347
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-17 19:34:54 +00:00
Michael Niewöhner 1d7b7f6e7a mb/system76/lemp9: move HDA options into devicetree
Change-Id: Id4fc12896f89739d0ee2a47a42173693921da14e
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45132
Reviewed-by:  Felix Singer <felixsinger@posteo.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-17 19:24:30 +00:00
Shreesh Chhabbi 7fbcdb3f9a mb/volteer: Select USE_CAR_NEM_ENHANCED_V2 for Tigerlake QS based
platforms

BUG=b:145958015
TEST= Build Volteer coreboot and boot on Volteer Proto 2 and Delbin.

Cq-Depend:chrome-internal-review:3249528
Change-Id: I0ff896424ab23dba43075c44eb9b2c2c480ccbfb
Signed-off-by: Shreesh Chhabbi <shreesh.chhabbi@intel.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45456
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2020-09-17 19:04:28 +00:00
nick_xr_chen 5200063114 mb/google/volteer/variants/eldrid: Configure DP_HPD as PAD_NC
GPP_A19(DP_HPD1) and GPP_A20(DP_HPD2) were configured native function
(NF1) without internal pull-down which wrongly presents HPD interrupts.
This change configures GPP_A19 and GPP_A20 to be no connection and
disables DdiPort1Hpd and DdiPort2Hpd.

BUG=b:165893624, b:168090618

Signed-off-by: nick_xr_chen <nick_xr_chen@wistron.corp-partner.google.com>
Change-Id: I31b25be1c9248debf855435c7b688b358e2cd57e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45246
Reviewed-by: Scott Chao <scott_chao@wistron.corp-partner.google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-17 18:20:53 +00:00
Elyes HAOUAS 72fc9a3e26 src: Remove redundant <device/pnp_type.h>
When <device/pnp.h> is needed, it is supposed to provide <device/pnp_type.h>.

Change-Id: I0e479e2abdb6cfb8633840db2222ce5397fe7d55
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45403
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-17 13:22:44 +00:00
Elyes HAOUAS 4b683b85a8 src: Remove redundant <device/pnp_def.h>
When <device/pnp.h> is needed, it is supposed to provide <device/pnp_def.h>.
So remove redundant <device/pnp_def.h> includes.
I'll remove also <device/pnp_type.h> in a separate patch.

Change-Id: Ib9903ae456c32db4ba346020659c17c27a939e89
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45316
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-09-17 13:21:48 +00:00
Rob Barnes 28cb14bf13 soc/amd/picasso: Clean up legacy UART config
Clean up configuration of the legacy UART and add Kconfig options for
the mapping between UART and legacy I/O decode.

BUG=b:143283592
BUG=b:153675918
TEST=Linux detects an additional legacy serial port for each active MMIO
one if PICASSO_UART_LEGACY is selected.
BRANCH=zork

Signed-off-by: Rob Barnes <robbarnes@google.com>
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Id08ff6428d4019303ebb6e44e13aba480cf1fde2
Reviewed-on: https://chromium-review.googlesource.com/2037891
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40322
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2020-09-17 12:35:56 +00:00
Michael Niewöhner 60795784b7 soc/intel/cannonlake: fix GPIO community numbering in ACPI
This corrects the GPIO community numbers in CNL-LP ACPI code.

Change-Id: I9f13a28d3e8f427859570a4d209304ae8444efd9
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45209
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-17 10:36:31 +00:00
Subrata Banik 7938ebc7d7 soc/intel/common/block/chip: Refactor chip_get_common_soc_structure()
Found-by: Klocwork, Pointer soc_config is used uninitialized.

Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Change-Id: I7e2aa4ef23a68a2ec2ba9d55cf890a7f81e3e278
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45416
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-09-17 09:57:06 +00:00
Subrata Banik 754de4da37 soc/intel/common/block: Add NULL check for 'ctx' pointer
Found-by: Klocwork, Avoid NULL pointer (ctx) dereference.

Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Change-Id: I16015b538112e0b125b4a5e145c26263c456953c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45411
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-17 09:56:56 +00:00
CK Hu 804b3bd10f soc/mediatek/mt8192: Init PLL in bootblock
Signed-off-by: CK Hu <ck.hu@mediatek.com>
Change-Id: If16d244e07d9f369efd991132587a92e38200b45
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45395
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2020-09-17 06:56:55 +00:00
Weiyi Lu fd3c727ed9 soc/mediatek/mt8192: Add mtcmos init support
Using common mtcmos code to power on audio and display modules in SOC.

TEST=Boots correctly on MT8192EVB. Passes the status check at the end of
     mtcmos_power_on()

Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com>
Change-Id: Ie7bff831eecfc2b4d315a577f6ff86befc483eab
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45394
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-17 06:56:31 +00:00
Chris Wang 7ef7596569 mb/google/zork: Add dptc interface support for morphius
Add dptc interface in devicetree for morphius.
Set the STAPM parameters for tablet mode:

    dptc_enable = 1
    dptc_fast_ppt_limit = 24000
    dptc_slow_ppt_limit = 20000
    dptc_sustained_power_limit = 6000

BUG=b:157943445
BRANCH=zork
TEST=Build. check the setting changed.

Signed-off-by: Chris Wang <chris.wang@amd.corp-partner.google.com>
Change-Id: I4dac4b7e5157ad7ad407f42a6fc6b06eefbf3291
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45153
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-09-17 06:19:07 +00:00
Chris Wang e019bd910f ec/google/chromeec: Add dptc interface support
add the dptc interface support when system in tablet mode.
In some FP5/FT5 platform, which will have different power or thermal
parameters depends on different form factor.

BUG=b:157943445
BRANCH=Zork
TEST=Build. check the setting changed.

Signed-off-by: Chris Wang <chris.wang@amd.corp-partner.google.com>
Change-Id: I2be7942132cea474237f531021ad4fd9856b5050
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44265
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-17 06:18:59 +00:00
Chris Wang 4735b1c01b soc/amd/picasso: add dptc support
add dptc support for different power parameter on tablet/clamshell mode

The BIOS may choose to adjust power and/or thermal parameters at its own
discretion. The DPTC interface(DPTCi) ALIB Function adds flexibility by
allowing  the BIOS to request power state changes independently of specific
 events.

BUG=b:157943445
BRANCH=none
TEST=Build.Generated ASL code from SSDT by acipgen_dptci().check the setting changed.

Signed-off-by: Chris Wang <chris.wang@amd.corp-partner.google.com>
Change-Id: Icae94103f254f8fdb84e6ee0f5404fb09fa97b2d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43408
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-09-17 06:05:27 +00:00
Angel Pons 2ce386a3c2 soc/intel/common/block: Do not die if PRMRR size unsupported
If a given PRMRR size is not supported, do NOT brick people's devices.
We don't do that when PRMRRs aren't even supported anyway.

Change-Id: Ib917be873aedbc5e789bb0894fca335b5ee9e2c2
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45373
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2020-09-16 20:56:35 +00:00
Shelley Chen 2d90ddd2d2 region_file_update_data_arr: Modify region_file with array of buffers
Add region_file_update_data_arr, which has the same functionality as
region_file_update_data, but accepts mutliple data buffers.  This is
useful for when we have the mrc_metadata and data in non-contiguous
addresses, which is the case when we bypass the storing of mrc_cache
data into the cbmem.

BUG=b:150502246
BRANCH=None
TEST=reboot from ec console.  Make sure memory training happens.
     reboot from ec console.  Make sure that we don't do training again.

Change-Id: Ia530f7d428b9b07ce3a73e348016038d9daf4c15
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45407
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-16 16:02:54 +00:00
Felix Held a79e01bf71 soc/amd/picasso/data_fabric: make register number parameter unsigned
The register number is always non-negative, so it should be an unsigned
type.

Change-Id: I6b6df5a41fe58efc53eaa87c01b88426ea8daa6e
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45430
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-09-16 14:47:15 +00:00
Felix Held bf90b14d6a soc/amd/picasso/data_fabric: include types.h
data_fabric.c uses types from stdint.h, but doesn't include stdint.h
directly, so replace the inclusion of stdbool.h with types.h which
includes both stdbool.h and stdint.h.

Change-Id: I4c1ea444e50218cf19fc8fff499929336265bd03
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45429
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com>
2020-09-16 14:47:04 +00:00
Marc Jones 5cb7599ca1 xeon_sp/skx: Reorder pci_devs.h
Reorder to be similar to cpx/include/soc/pci_devs.h.
We may be able to merge the files in the future.

Checked TiogaPass with BUILD_TIMELESS=1

Change-Id: I939707cc9e58e23f053156f40df4c21a6072570b
Signed-off-by: Marc Jones <marcjones@sysproconsulting.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45220
Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-16 10:18:59 +00:00
Marc Jones 8015482f67 xeon_sp/cpx/pci_devs.h: Remove duplicate defines
Change-Id: I8fc4e07269175eb2f40655b828e340697a9a892a
Signed-off-by: Marc Jones <marcjones@sysproconsulting.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45219
Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-16 10:18:44 +00:00
Weiyi Lu 0fed84b8c4 soc/mediatek: move power status bits under each chip
The power status bits of display and audio of MT8192 are different
from the bits of MT8173 & MT8183, so move those under each chip.

Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com>
Change-Id: Iaa211b8db733d8aa52d93af9e507042bf0984d55
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45393
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2020-09-16 07:48:20 +00:00
Pandya, Varshit B d121a117cc mb/google/dedede: Replace static Camera ACPI by driver for WDoo
This change updates devicetree to enable SSDT generation for world
facing camera and user facing camera of Waddledoo. Also reverts DSDT
changes related to both the camera.

Signed-off-by: Pandya, Varshit B <varshit.b.pandya@intel.com>
Change-Id: Ib7e875d297c04f35d4e980ff33d9a3767d2910ac
Signed-off-by: Sugnan Prabhu S <sugnan.prabhu.s@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44397
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
2020-09-16 07:16:19 +00:00
Pandya, Varshit B cd91db953c drivers/intel/mipi_camera: Add compatible field for NVM
Add compatible field for NVM
Make PRP0001 as default HID if device type is INTEL_ACPI_CAMERA_NVM

Signed-off-by: Pandya, Varshit B <varshit.b.pandya@intel.com>
Change-Id: Iad7afa7b3170982eb5d6215e766f3e98f7a89213
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45091
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
2020-09-16 07:16:09 +00:00
Ian Feng c410542007 mb/google/dedede/var/madoo: Enable keyboard backlight feature
This enables the keyboard backlight feature in ACPI for madoo.

BUG=b:167943993
TEST=Verified 'kbd_backlight' shows up in the '/sys/class/leds '.

Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
Change-Id: I11531699cb650b96becae5c1bec9f89c48b6bea0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45330
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2020-09-16 07:15:05 +00:00
Caveh Jalali 8274c2926f drivers/spi/tpm: Improve error checking
This adds error checking in paths that previously ignored TPM
communication errors. We hit this case occasionally during "Checking
cr50 for pending updates"; previously we would go down this path and
eventually time out using MAX_STATUS_TIMEOUT, which is 2 minutes.
Now, we detect the failure and return with an error indication instead
of timing out after a long time. The root cause of the communication
error is an open issue.

BUG=b:168090038
TEST=booted on volteer, observed error handling when
	"Checking cr50 for pending updates" fails.

Signed-off-by: Caveh Jalali <caveh@chromium.org>
Change-Id: Ia8a1202000abce1857ee694b06b1478e6b045069
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45232
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jes Klinke <jbk@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-09-16 07:14:40 +00:00
Angel Pons 0f651650f3 drivers/aspeed/common: Reduce severity of `EDID not found` log message
Servers often run headless, so a missing EDID isn't a problem. However,
we still need to initialize a framebuffer for the BMC's KVM function.

Reduce the log level to BIOS_INFO to avoid confusion.

Change-Id: Ice17bf6fdda0ce34e686dbf8f3a1fa92ba869d7c
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45234
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2020-09-16 07:14:15 +00:00
Rob Barnes e5aa5ae1ba soc/amd/picasso: Convert DDR4 MHz to MT/s correctly
Memory speed is given as an integer in MHz. In some cases it has
an implicit fractional speed, so simply multiplying by 2 is not
sufficient.

Use method from dram/ddr4.c instead.

BUG=b:167155849
TEST=Boot ezkinil, check output of 'mosys memory spd print all'
     and dmidecode -t17
BRANCH=Zork

Signed-off-by: Rob Barnes <robbarnes@google.com>
Change-Id: Icc77c21932c68ee9f0ff0b8e35ae7b1a3732b322
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45177
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-09-16 03:25:28 +00:00
Rob Barnes a01ee36288 device/dram: Add method for converting MHz to MT/s
Add method for converting DDR4 speed in MHz to MT/s. Checks that MHz is
within a speed grade range.

BUG=b:167155849
TEST=ddr4-test unit test
BRANCH=Zork

Change-Id: I1433f028afb794fe3e397b03f5bd0565494c8130
Signed-off-by: Rob Barnes <robbarnes@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45343
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-09-16 03:24:50 +00:00
Lucas Chen fcd7d0518c zork/var/ezkinil: Fix Touchscreen doesn't work on v3.6x rework board
The gpio90 EN_PWR_TOUCHSCREEN had been set to PAD_GPO(GPIO_90, LOW), but
addtional PAD_NC(GPIO_90) cause enable fail. remove it for issue fixed.

BRANCH=zork
BUG=b:168580357
TEST=Check Touchscreen function work

Signed-off-by: Lucas Chen <lucas.chen@quanta.corp-partner.google.com>
Change-Id: Id94dd63ba51759cebaf17779a5e659dbe0f1807f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45415
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-16 02:04:25 +00:00
Ravi Kumar Bokka 9c0b8ef83c trogdor: invoke new watchdog function before qclib runs
Signed-off-by: Ravi Kumar Bokka <rbokka@codeaurora.org>
Change-Id: Ia76323c749a9ba71cc752a91c968aeacc11e0093
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45212
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-16 00:44:18 +00:00
Ravi Kumar Bokka 6fde4c56b0 sc7180: report hardware watchdog reset after reboot
add WATCHDOG_TOMBSTONE in memlayout.ld

Change-Id: I57ece39ff3d49f2bab259cbd92ab039a49323119
Signed-off-by: Ravi Kumar Bokka <rbokka@codeaurora.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44868
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2020-09-16 00:44:09 +00:00
Felix Held 336ed66e35 soc/amd/stoneyridge/acpi/sb_pci0_fch: remove duplicate I/O range
This I/O region is already covered by the range declared right above the
deleted one.

Change-Id: I8b8ff3385bbba8e69101ee2c5a5cb39c8f996b94
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45369
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-15 19:31:54 +00:00
Felix Held 4ed3116f33 soc/amd/picasso/acpi/sb_pci0_fch: remove duplicate I/O range reservation
This I/O region is already covered by the range declared right above the
deleted one.

TEST=Linux stops complaining about overlapping I/O regions.
BRANCH=zork

Change-Id: I149fb0dc85bfe721a6b0d81e4e9c197194718876
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45368
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-15 19:31:48 +00:00
Patrick Rudolph a1ef21301b nb/intel/ironlake/raminit: Work around compiler bug
This fixes commit e1d1fe454c
initialize 'reply.command'.

The compiler now optimized away the final condition, that checks
the result of heci message, resulting in a binary that always
calls die().

Fix that behaviour by using volatile.
Tested on Lenovo T410: Boots again into Linux.

Change-Id: I63cffc8812bd22695c01bf57283ca593b12e3d87
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45174
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-09-15 18:03:26 +00:00
Subrata Banik 292afef2fb soc/intel/alderlake/romstage: Do initial SoC commit till romstage
List of changes:
1. Add required SoC programming till romstage
2. Include only required headers into include/soc
3. Add SA EDS document number and chapter number
4. Fill required FSP-M UPD to call FSP-M API

Change-Id: I4473aed27363c22e92e66cc6770cb55aae83e75c
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45192
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-09-15 15:13:50 +00:00
Subrata Banik eb17b475c8 mb/intel/jasperlake_rvp: Fix wrong comments for ECT
Disable -> Enable

Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Change-Id: Iccefb02fa9bf9507b9e679b3fba35c5c28d677a1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45338
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-09-15 15:13:06 +00:00
Jason Glenesk 201acca634 acpi: Correct sizes for ACPI data fields
Correct sizes of Count, Type, and Latency data field in _CST object to
integer, byte, word, respectively. Correct size of NumEntries data field
in _CSD object to integer.

BUG=b:155307433
TEST=Boot Morphius and dump SSDT _CST and _CSD objects. Confirm that
sizes written conform to ACPI_6_3_May16.pdf ACPI specification.
BRANCH=Zork

Change-Id: I356b46f2fa787e18442a66280b6545a3b525a08b
Signed-off-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45339
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-15 13:41:58 +00:00
Patrick Rudolph 11c1b94d03 soc/intel/common/block/cpu: Fix boot failure
This fixes commit 1b89f5e "Guard options with if-blocks".

The code no longer returns if SGX is disabled, but as the PRMRR
configuration is missing it runs into die().

Tested on Prodrive Hermes: Boots again into Linux.

Change-Id: I6d32ca32b1b53767b2db91305103cd532823a5ca
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45344
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-09-15 09:17:58 +00:00
V Sowmya 186250f68e common/block/pmc: Add a check to program the PchPmPwrCycDur
This patch adds a check to avoid violating the PCH EDS recommendation
that the PchPmPwrCycDur will never be smaller than the the SLP_Sx
assertion widths.

This code was initially added for cannonlake and now moving it to common
code since the same check will be used to program the PchPmPwrCycDur
for Jasperlake and Tigerlake.

Change-Id: Ie7d5f54939c5eb1f885d303f75a04958b9d77f4d
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45028
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-15 07:02:04 +00:00
Ren Kuo 98b0a98891 mb/google/dedede/var/magolor: Add touch screen devices
add the magolor touch screen ctrl devices:
1)elan 6915
2)elan 5012
3)raydium RM32680

BUG=b:166711761
BRANCH=None
TEST=build firmware and verify the touch functions on DUT

Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
Change-Id: Icd2963317e858f7d35c937e45cd6f3e556bbb953
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45227
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Henry Sun <henrysun@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-15 07:01:29 +00:00
Furquan Shaikh b0334e13ba mb/google/zork: Fix FPMCU_INT_L configuration
Fingerprint interrupt (FPMCU_INT_L) is level triggered and not edge
triggered. Also, we are using GEVENT for wake from fingerprint and
not the GPIO IRQ wake. Thus, the irq property exposed in ACPI tables
does not need to be set to indicate wake for the IRQ.

This change updates GPIO table to configure the pad as level triggered
and drops the wake attribute for irq_gpio in overridetree.

BUG=b:165612778
BRANCH=zork
TEST=Verified that fingerprint still works in S0 and to wake device
from S3.

Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: I9007e5b0882ac1a6770db52d651218998f6d750d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45307
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-09-15 03:57:43 +00:00
Ravi Kumar Bokka 5ed3cb99ac chromeos: Provide common watchdog reboot support in romstage
Signed-off-by: Ravi Kumar Bokka <rbokka@codeaurora.org>
Change-Id: I2a1f1411e9d58a0738e0e8057f5b1ad049bf03e3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45213
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-15 01:09:38 +00:00
Taniya Das 4236187dea sc7180: clock: Remove unwanted QUPv3 Frequency
As the UART clock frequency is no longer required by the UART
driver, remove the unwated frequency.

Tested: Compile and boot up testing.

Change-Id: I137682b3ca45481ad34ac8ddb5cd308444f752a7
Signed-off-by: Taniya Das <tdas@codeaurora.org>
Signed-off-by: Ravi Kumar Bokka <rbokka@codeaurora.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45198
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2020-09-15 01:07:27 +00:00
Roja Rani Yarubandi dcf80ab025 sc7180: Remove QcLib specific changes from CB UART
To achieve 115200 baudrate QcLib reconfigures UART frequency
with the lowest supported frequency from QUP clock table.
With this console logs were getting corrupted at qclib stage.

In ChromeOS coreboot, baudrate is configuarable using Kconfig.
QcLib should not assume the baudrate and reconfigure any UART
register once after the configuration is done in coreboot.

To fix the issue QcLib done the changes to not to reconfigure
any UART registers. Hence clock_configure_qup() is not required
in coreboot UART driver.

Signed-off-by: Roja Rani Yarubandi <rojay@codeaurora.org>
Change-Id: I2531b64eddfa6e877f769af0d17be61f5e4d0c35
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42095
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2020-09-15 01:07:17 +00:00
Nico Huber 308540de80 nb/intel/ironlake: Reserve gap betwen TSEG and BGSM
There may be a gap between TSEG and the graphics stolen memory due to
the alignment done in `raminit.c`. If we allocate MMIO resources in
this range, it misbehaves unpredictably, so reserve it.

TEST=Booted Thinkpad X201s, allocated resources are above TOLUD.

Change-Id: If305e9751ebf4edc945cf038ed72698f3696e52d
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45325
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-14 20:15:06 +00:00
Nico Huber 08e8e47d03 nb/intel/ironlake: Use an `index` variable for resources
Change-Id: Ic587231b57c51db592c1647de138a67c55161e58
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45324
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-09-14 20:14:47 +00:00
Elyes HAOUAS 66039a5cb8 src/mainboard: Remove unused include <device/pnp_ops.h>
Change-Id: I278fb20aa176bb09f1ff135fdfd732f0096d3808
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45313
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-09-14 19:38:14 +00:00
Elyes HAOUAS 864d1cfeca mb/amd/olivehill/bootblock.c: Add missing <arch/io.h>
Change-Id: I75ea4fc71cf22e5ad547329db2451342cee528b2
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45314
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-09-14 19:36:58 +00:00
Elyes HAOUAS b4093dca8d src/superio: Remove unused <device/pnp_def.h>
Change-Id: I835e8786b84ec16889fd08f566328bc7a0a60c90
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45312
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-09-14 19:36:27 +00:00
Elyes HAOUAS 79a3de16a1 src/{device,include}: Use PNP_IDX_EN instead of magic number
Change-Id: I68590605e261ecaace9f3cea28cfa6ec3b913a8a
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44835
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-09-14 19:34:11 +00:00
Shelley Chen 475978875d drivers/elog: Remove ELOG_PRERAM config
This change is being done for the following reasons:
1.  The CONFIG_ELOG_PRERAM is unused.
2.  We need to pull in elog.c into romstage because we are pulling the
    mrc_cache_stash_data function into romstage.
3.  Furquan says that we can rely on the linker to optimize out the
    unused 4KiB buffer in the early stages of boot, which allows us to
    get rid of the ELOG_PRERAM config.

BUG=b:117884485, b:150502246
BRANCH=None
TEST=./util/abuild/abuild -p none -t GOOGLE_NAMI -x -a -v

Change-Id: Id76cabc38e41e9bf79e1580a530c871a4ecef4ec
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45303
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-14 18:23:23 +00:00
Josie Nordrum c3cc158408 lib/fmap: add ENV_SMM check to setup_preram_cache
Add check in setup_preram_cache to return if ENV_SMM is true.
This avoids false warning that post-RAM FMAP is accessed too early
caused by ENV_ROMSTAGE_OR_BEFORE evaluation in SMI handler.

BUG=b:167321319
BRANCH=None
TEST=None

Signed-off-by: Josie Nordrum <josienordrum@google.com>
Change-Id: I3a4c199c42ee556187d6c4277e8793a36e4d493b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45274
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-09-14 16:01:42 +00:00
Subrata Banik 7ad46df850 soc/intel/common/block: Use pci_dev_request_bus_master for BM enabling
Enabling Bus Master isn't required by the hardware, so we shouldn't need
to enable it at all. However, some payloads do not set this bit before
attempting DMA transfers, which results in boot failures.

Replace static sata_final() implementation for BM enabling with generic
pci_dev_request_bus_master() function.

This allows the user to control through Kconfig whether Bus Master
should be enabled.

TEST=Able to boot to OS from SATA device on CML platform.

Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Change-Id: Icd086184fd6fa9c03c806c857f13fad5a9e78a3e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45320
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-09-14 12:07:04 +00:00
Subrata Banik 9fec889e82 soc/intel/{cnl,icl,jsl,tgl}: Clean up chip.h
Removed unused header files in chip.h

Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Change-Id: Idb9b1ed23df3dbb9dad4d36651064c21a4d913fc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45322
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2020-09-14 12:06:39 +00:00
Subrata Banik c9d598a581 soc/intel/jasperlake: Clean up iomap.h and systemagent.h
List of changes:
1. Convert inconsistent white space into tab.
2. Group together all MCHBAR offset macros.

Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Change-Id: Ief13406b0116ce0f0b7472e5b133b3fac06f6e27
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45321
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2020-09-14 11:53:27 +00:00
Michael Niewöhner 8ca0b21060 soc/intel/cnl: Add ACPI support for PMC core OS driver
PMC core OS driver (intel_pmc_core.c in linux kernel) provides debug
hooks to developers and end users to quickly figure out why their
platform is not entering a deeper idle state such as S0ix.

Include the common pmc.asl added in commit 957481c.

Test: PMC gets detected by Linux kernel module.

Change-Id: Ibf7c8ba7449df15c2ca30d23791e17fc878204f2
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45318
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-14 11:51:02 +00:00
Idwer Vollering 3c5b803bdb util/cbfstool: extend includes in commonlib
Certain non-Linux OSes require an include file in different
places.

Build tested on Linux, FreeBSD.

Change-Id: Icd81c2a96c608589ce2ec8f4b883fd4e584776b1
Signed-off-by: Idwer Vollering <vidwer@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38648
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-14 07:10:53 +00:00
Elyes HAOUAS 563fc0889f src/include: Drop unneeded empty lines
Change-Id: Ie325541547ea10946f41a8f979d144a06a7e80eb
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44611
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-09-14 07:09:41 +00:00
Raul E Rangel 7c79d8302b soc/amd/picasso: Move sd_emmc_config into emmc_config struct
I plan on adding another eMMC parameter. This refactor keeps the config
contained in a single struct.

BUG=b:159823235
TEST=Build test

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I4b57d651ab44d6c1cad661d620bffd4207dfebd4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45095
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-09-14 07:09:23 +00:00
Ravi Sarawadi 73cd3e704f mb/google/delbin: Configure DP_HPD as PAD_NC and disable DdiPortHpd
GPP_A19(DP_HPD1) and GPP_A20(DP_HPD2) were configured native function
(NF1) without internal pull-down which wrongly presents HPD interrupts.
DP_HPD had been removed for EVT design as those events are through eSPI.
This change configures GPP_A19 and GPP_A20 to be no connection and
disables DdiPort1Hpd and DdiPort2Hpd.

BUG=b:162566436
TEST=Booted to kernel and verified no kernel HPD pins assertion message
on Delbin board.

Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com>
Change-Id: Ifdef8ee438276678258b75d2fb70c6dfc7ee0a33
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45031
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
2020-09-14 07:09:11 +00:00
John Su 47c4bf5571 mb/google/octopus/variants/fleex: Add G2Touch touchscreen support
BUG=b:167297664
BRANCH=octopus
TEST=build fleex, and check touchscreen can work

Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Change-Id: I910681c258ff5487830e795a8bd08c66be69b1d4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44980
Reviewed-by: Justin TerAvest <teravest@google.com>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Reviewed-by: Marco Chen <marcochen@google.com>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Henry Sun <henrysun@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-14 07:08:56 +00:00
Kangheui Won 5f027fa4c2 soc/amd/picasso: copy local info to transfer buf
We added transfer_info_struct to contain various information about
memory region we pass from PSP to x86 in commit 0c12abe462.

This should be at the start of transfer region but we only manipulated
it as local variable and didn't put data into the region, resulting
garbage data for transfer_info when x86 tries to read it.

Copy the content of local variable to beginning of _transfer_buffer
before requesting transfer to PSP so coreboot on x86 can access it.

BUG=b:159220781
BRANCH=zork
TEST=check transfer_info_struct is correctly populated on romstage

Signed-off-by: Kangheui Won <khwon@chromium.org>
Change-Id: I14bc34e6af501240a6f633db3999a7759e88d60b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44751
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-14 07:08:39 +00:00
Angel Pons 8840bcfa86 include/superio/hwm5_conf.h: Fix copy-pasted comments
Comments say `port`, but the actual function signature uses `base`.

Change-Id: I28a2f24a9701aec2fb990ca2f38e5f2794e15f0c
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45226
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-14 07:08:03 +00:00
Karthikeyan Ramasubramanian 410af46cd6 mb/google/dedede/var/boten: Add audio configuration
Add configuration for ALC5682 headphone jack and ALC1015 speaker
amplifier. Also turn on the HDA PCI device.

BUG=b:161667665
TEST=Build the boten board and verified the audio functionality.

Change-Id: I835db854543e6282c102c86a7073b432fd89d0a5
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44920
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-14 07:07:24 +00:00
Angel Pons 19b2599cb5 sb/intel/lynxpoint/acpi: Do not determine PCH type at runtime
Both PCH types are very different, and mixing the code for both together
isn't useful. Make `ISLP` return a constant, so that IASL can fold it.

Change-Id: I6222d6661115d444d4dad0217c2d376dc551465c
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45048
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-14 07:07:12 +00:00
Angel Pons d9f1b04ec5 sb/intel/lynxpoint: Do not determine PCH type at runtime
Both PCH types are very different, and mixing the code for both together
isn't useful. First of all, inline `pch_is_lp` to return a constant.
This allows the compiler to optimize out unused code, which results in
smaller executables. For the Asrock B85M Pro4, it's about 2.5 KiB less.

Subsequent commits will further split the southbridge code.

Change-Id: Iba904acf64096478d1b76ffd05a076f0203502f8
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45047
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-14 07:07:04 +00:00
Angel Pons 78c615c332 mb/ocp/deltalake: Drop redundant `select FSP_CAR`
This is selected by Xeon SP Kconfig already.

Change-Id: If1ef7f86b27d7be74912c9ad1f9c1efbda6233e5
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45224
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
2020-09-14 07:06:40 +00:00
Jonathan Zhang 9366885a42 soc/intel/xeon_sp/cpx: display FSP_PREV_BOOT_ERR_SRC_HOB
Before MRC code execution, FSP interrogates EMCA MSR registers and other
registers to see if there are fatal errors happened during previous boot
session. If there are, error records are saved into
FSP_PREV_BOOT_ERR_SRC_HOB.

When the value of Length field of FSP_PREV_BOOT_ERR_SRC_HOB is 2, that means
the HOB does not contain any valid error record.

TESTED=Injects MCE error through cscript, reboot into OS, check boot log:
0x75904d70, 0x00000400 bytes: HOB_TYPE_GUID_EXTENSION
        5138b5c5-9369-48ec-5b9738a2f7096675: FSP_PREV_BOOT_ERR_SRC_HOB_GUID
================ PREV_BOOT_ERR_SRC HOB DATA ================
hob: 0x75904d88, Length: 0x42
         MCBANK ERR INFO:
                 Segment: 0, Socket: 0, ApicId: 0x0
                 McBankNum: 0x3
                 McBankStatus: 0xfe00000000800400
                 McBankAddr: 0xf0ff
                 McBankMisc: 0xfffffff0
         MCBANK ERR INFO:
                 Segment: 0, Socket: 0, ApicId: 0x0
                 McBankNum: 0x4
                 McBankStatus: 0xfe00000000800400
                 McBankAddr: 0xfff0
                 McBankMisc: 0xfffffff0
0x75904d88: 42 00 01 00 00 00 00 00 03 00 00 04 80 00 00 00  B...............
0x75904d98: 00 fe ff f0 00 00 00 00 00 00 f0 ff ff ff 00 00  ................
0x75904da8: 00 00 01 00 00 00 00 00 04 00 00 04 80 00 00 00  ................
0x75904db8: 00 fe f0 ff 00 00 00 00 00 00 f0 ff ff ff 00 00  ................
0x75904dc8: 00 00

Change-Id: Idbace4c2500440b3c1cf2628dd921ca1a989ae81
Signed-off-by: Jonathan Zhang <jonzhang@fb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44974
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-14 07:05:49 +00:00
Jonathan Zhang 7f4395f40e src/vendorcode/intel/fsp/fsp2_0/cpx-sp: add prev boot error info HOB header file
PREV_BOOT_ERR_SRC_HOB is generated by CPX-SP FSP by interrogating
error status registered (such as MCA MSRs) to list fatal errors happened
during the previous boot session.

The header file supports 3 different error source types. CPX-SP FSP
supports only McBankType.

Change-Id: I9b88af17075b98e88c7e94e55fea37627ec03cd0
Signed-off-by: Jonathan Zhang <jonzhang@fb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44973
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-14 07:05:41 +00:00
Caveh Jalali 3b616e4bde mb/google/volteer: Fix GPP_E12 definition
GPP_E12 should not be defined in the baseboard as its use is
determined by the variant. For legacy reasons, we still have GPP_E12
defined in early_gpio but should not. Malefor and volteer* have the
same GPP_E12 definition, but that is a misconfiguration. I think that
was a copy-paste that slipped through the reviews.

BUG=b:157597158
TEST=volteer2 boots to the OS

Change-Id: Ic3ef864827aa94b0b96e335565119f3d5d008837
Signed-off-by: Caveh Jalali <caveh@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45197
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2020-09-14 07:04:45 +00:00
David Wu a545d30831 mb/google/volteer/var/voxel: Update DPTF parameters and TCC offset
1. Set tcc offset to 5 degree celsius
2. Apply the DPTF parameters received from the thermal team.

BUG=b:167523658
TEST=build and verify by thermal team

Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: I01a6fc5bd959798c8dd423df3907c69c883733e8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45111
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-09-14 07:04:34 +00:00
Tim Wawrzynczak a5cb5649fb mb/google/volteer: Refactor baseboard devicetree
Clean up the DPTF section of the baseboard devicetree; this makes
overrides simpler, as not necessarily all of the fields need to be
overridden.

Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: Iad46fd02f7602c9419d7c3674b0d2b6f5add9a93
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45179
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-09-14 07:04:28 +00:00
Sumeet R Pawnikar 426e07aaf2 mb/google/dedede/variants/drawcia: Increase PL2 value from 15W to 20W
Jasper Lake SoC supports PL2 (Power Limit2) as 20W. Increase PL2 value from 15W to 20W.

BRANCH=None
BUG=b:166656373
TEST=Built and tested on drawlat system

Change-Id: I82d6792907bb1c88cc9dd57d1eaeda8421c12fb2
Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45162
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-14 07:04:07 +00:00
Anil Kumar 033038fd48 soc/intel/tigerlake: Increase PRERAM_CBMEM_CONSOLE_SIZE to 8KB
This patch increases PRERAM_CBMEM_CONSOLE_SIZE from 5KB to 8KB to fix
cbmem buffer overflow issue.

Bug=None
Branch=None
Test=Boot TGLRVP and check cbmem -c | grep 'CBFS: Locating' lists all stages

Signed-off-by: Anil Kumar <anil.kumar.k@intel.com>
Change-Id: I2393cc83008211be8e6a2ca7a1e41a7e9d92caf0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45183
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-14 07:03:47 +00:00
John Zhao 623da4bc5d mb/google/volteer: Add error handling
Coverity detects missing error handling after calling function
tlcl_lib_init. This change checks the function tlcl_lib_init return
value and handles error properly.

Found-by: Coverity CID 1432491
TEST=None

Signed-off-by: John Zhao <john.zhao@intel.com>
Change-Id: Ife38b1450451cb25e5479760d640375db153e499
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45176
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-09-14 07:03:33 +00:00
David Wu d944f1797f mb/google/volteer: Enable EC software sync
Enable EC software sync for terrador and todor

BUG=None
TEST=emerge-volteer coreboot chromeos-bootimage

Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: I8c463eadd19d99dc04923f7400560cf7ba4b8101
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45186
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
2020-09-14 07:03:20 +00:00
Shreesh Chhabbi 121bc7a674 soc/intel/tigerlake: Select USE_CAR_NEM_ENHANCED_V2 for tigerlake
Selects Cache QoS mask MSR programming flow for Tigerlake SoC.

BUG=b:145958015
TEST= Build and boot to Chrome OS on TGL-UP3 RVP.
Recipe used:
1. Patch https://review.coreboot.org/c/coreboot/+/43494 that
implements calculation of CQOS mask dynamically based on stack
size usage & incorporates Tigerlake SoC specific programming flow.
2. QS Engineering Microcode based on 0x56 Official Microcode with
LLC CQOS change.
3. QS SoC Part

Signed-off-by: Shreesh Chhabbi <shreesh.chhabbi@intel.corp-partner.google.com>
Change-Id: I602d93eb4f8243ec49993b00691140d9a6cf5733
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45094
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-09-14 07:02:44 +00:00
Aamir Bohra c1d227d312 soc/intel/common/cpu: Update COS mask calculation for NEM enhanced mode
Update the COS mask calculation to accomodate the RW data as per SoC
configuration. Currently only one way is allocated for RW data and
configured for non-eviction. For earlier platform this served fine,
and could accomodate a RW data up to 256Kb. Starting TGL and JSL, the
DCACHE_RAM_SIZE is configured for 512Kb, which cannot be mapped to a
single way. Hence update the number of ways to be configured for non-
eviction as per total LLC size.

The total LLC size/ number of ways gives the way size. DCACHE_RAM_SIZE/
way size gives the number of ways that need to be configured for non-
eviction, instead of harcoding it to 1.

TGL uses MSR IA32_CR_SF_QOS_MASK_1(0x1891) and IA32_CR_SF_QOS_MASK_2(0x1892)
as COS mask selection register and hence needs to be progarmmed accordingly.

Also JSL and TGL platforms the COS mask selection is mapped to bit 32:33
of MSR IA32_PQR_ASSOC(0xC8F) and need to be updated in edx(maps 63:32)
before MSR write instead of eax(maps 31:0). This implementation corrects
that as well.

BUG=b:149273819
TEST= Boot waddledoo(JSL), hatch(CML), Volteer(TGL)with NEM enhanced
      CAR configuration.

Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Change-Id: I54e047161853bfc70516c1d607aa479e68836d04
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43494
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shreesh Chhabbi <shreesh.chhabbi@intel.corp-partner.google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-09-14 07:02:26 +00:00
Felix Held 828a36e325 soc/amd/picasso/chip: fix typo in acp_pme_enable
That devicetree setting is about the Audio Co-Processor and not ACPI.

BRANCH=zork

Change-Id: I7f376371ee094392d4434340c77f0fc8d0d8e4e1
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45300
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2020-09-13 00:04:10 +00:00
Felix Held 6c61b4b3ac soc/amd/picasso/aoac: make AOAC device number unsigned
The AOAC device number is never negative, so make it unsigned.

BRANCH=zork

Change-Id: I3e0d15a646f02da5767504471961d5d9f8f28bea
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45308
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-13 00:03:34 +00:00
Felix Held 2617073ee0 soc/amd/picasso/uart: make AOAC device ID in uart_enable unsigned
This change is separate from CB:45308 to only have the directly UART-
related changes in this patch train.

BRANCH=zork

Change-Id: Ie587fdbd1e6229c1374fce3568c6a361577dc6c4
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45310
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-09-13 00:01:38 +00:00
Felix Held 2e800038ab soc/amd/picasso/uart: add missing types.h include
BRANCH=zork

Change-Id: I51923d72a2ad8dceeef11e15fb6765262dd514d9
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45309
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-09-13 00:01:12 +00:00
Angel Pons 1b89f5eeab soc/intel/common/block/*/Kconfig: Guard options with if-blocks
The usual structure of these files is a global enable symbol, usually
followed by an if-block which contains all other dependent symbols.

Use this instead of having a `depends on` line to each symbol. Guard all
symbols, even if they originally were not guarded, since they don't do
anything useful unless the global enable option is selected.

Change-Id: If5347187b07a46192f0063011ab197b5047f555f
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45043
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-12 23:00:12 +00:00
Felix Held 4b58d14fa7 soc/intel/denverton_ns/uart_debug: include header for uart_platform_base
Include console/uart.h for the declaration of uart_platform_base instead
of declaring the function in the source file.

Change-Id: Ib72d8884f27e93cec058dbcda404dd6908de1981
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45295
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-09-12 15:00:07 +00:00
Felix Held e3a1247b15 include/console/uart: make index parameter unsigned
The UART index is never negative, so make it unsigned and drop the
checks for the index to be non-negative.

Change-Id: I64bd60bd2a3b82552cb3ac6524792b9ac6c09a94
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45294
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-09-12 14:59:33 +00:00
Felix Held 8395165eee soc/amd/picasso/uart: make index parameters unsigned
The UART index is never negative, so make it unsigned and drop the check
for the index to be non-negative.

BRANCH=zork

Change-Id: I38b5dad87f8af4fbe8ee1d919230efe48f68686c
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45292
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-09-12 14:59:12 +00:00
Christian Walter c92524d488 mb/ocp/deltalake: Enable TPM2
Change-Id: I6eaaf80dd2bd69096574ab967ec0c6738b05903b
Signed-off-by: Christian Walter <christian.walter@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45268
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-09-12 14:30:27 +00:00
Michael Büchler 70fea013c7 cpu/intel/model_1067x: enable PECI
This is required for Super I/Os to be able to read the CPU temperature
through PECI.

On 45nm Core 2 CPUs (Wolfdale, Yorkfield) it is not enabled by default.
This is probably related to erratum AW67 "Enabling PECI via the PECI_CTL
MSR incorrectly writes CPUID_FEATURE_MASK1 MSR". The suggested
workaround is "Do not initialize PECI before processor update is
loaded". Since coreboot performs microcode updates before running this
code it should not cause any trouble. It was tested on a Core 2 Duo
E8400, stepping E0.

PECI is already enabled by default on older (65nm) CPUs. Tested: Pentium
Dual-Core E2160.

See commit edac28ce65 for the same change
on cpu/intel/model_6fx.

Signed-off-by: Michael Büchler <michael.buechler@posteo.net>
Change-Id: I5a3ec033bd816665af4ecc82f7b167857cd7c1b6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45184
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-09-12 10:50:33 +00:00
Elyes HAOUAS eea0657044 mb/msi/ms7721: Use PNP_IDX_EN instead of magic number
Change-Id: Ica66ad6da61376f64f9d24de015f84d250327d66
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44840
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-09-11 22:36:37 +00:00
Elyes HAOUAS c33f6e047f mb/ibase/mb899: Use 'PNP_IDX_*' macros instead of magic number
Change-Id: I1e543f8ff701fa20eaaee601ef54f0b056e61909
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44832
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-09-11 22:33:28 +00:00
Elyes HAOUAS 92c4bc19e9 mb/kontron/ktqm77: Use 'PNP_IDX_*' instead of magic numbers
Change-Id: Ic4f51a59524bacb374d90c5620f810e96d7b8eb2
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44839
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-09-11 22:32:52 +00:00
Bob Moragues c06c0ce559 strongbad / coachz : Add Initial Support
BUG=b:162409909
BUG=b:164196066
BRANCH=NONE
TEST=Verify build of strongbad target

Signed-off-by: Bob Moragues <moragues@chromium.org>
Change-Id: If83bd2c8f25fdd3c9625f40121e55c3c922a66fe
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45276
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-11 22:32:34 +00:00
Elyes HAOUAS 600e70dd52 mb/kontron/986lcd-m: Use ''PNP_IDX_*' instead of magic numbers
Change-Id: Ic7c1b4defa8c65ed739b1cf3861087cd53cd997c
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44838
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-09-11 22:32:28 +00:00
Elyes HAOUAS e1b1bc94c8 mb/biostar/am1ml: Use 'PNP_IDX_*' instead of magic numbers
Change-Id: I5eaf33558e14f63045928215d88d2ad2554fdbf2
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44836
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-09-11 22:24:27 +00:00
Elyes HAOUAS 9b54dfa1d0 src/superio: Use 'PNP_IDX_*' macros instead of magic numbers
Change-Id: I2f8d6d9e8b6e84bb6c2b4e73b0fbeca476130d05
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44833
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-09-11 22:19:38 +00:00
Karthikeyan Ramasubramanian aa03f30e6e mb/google/dedede/var/drawcia: Remove debug statement with NULL pointer
The debug statement to print WiFi SAR file can potentially have a NULL
pointer. Also the debug statement does not add much value. Hence remove the
debug statement.

BUG=b:165613510
TEST=Build and boot the drawcia board to OS.

Change-Id: I710240f5e965f523fb8ac55a67880e1cbf9abd48
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45298
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-09-11 19:51:54 +00:00
Elyes HAOUAS ad7c8ffba9 src/ec: Drop unneeded empty lines
Change-Id: I1955390fcceeb42ecb644ac74541b7e9dd25320f
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44610
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-09-11 17:07:03 +00:00
Wisley Chen 8b70772ab4 mb/google/dedede/var/drawcia: Add Wifi SAR for drawcia
drawman/drawlat/drawcia share the same coreboot, and only drawcia is convertible.
Use tablet mode of fw config to decide to load custom wifi sar or not.

BUG=b:165613510
TEST=enable CHROMEOS_WIFI_SAR in config of coreboot,
emerge-dedede coreboot-private-files-baseboard-dedede coreboot chromeos-bootimage.

Change-Id: Ibcd498021e63d0a172c71c3d94b60b3a25973467
Signed-off-by: Wisley Chen <wisley.chen@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44661
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2020-09-11 15:50:39 +00:00
Wisley Chen 4b5998917e mb/google/dedede: Enable FW_CONFIG
Enable FW_CONFIG and add tablet mode field in devicetree

BUG=b:165613510
TEST=emerge-dedede coreboot

Signed-off-by: Wisley Chen <wisley.chen@quantatw.com>
Change-Id: I55e4c0d0b4aa2337c01773006d0b485fdcd91654
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45185
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2020-09-11 15:50:25 +00:00
Wisley Chen b68679bcdc mb/google/dedede: Add option to enable WiFi SAR configs
BUG=b:165613510
TEST=emerge-dedede coreboot

Change-Id: Ic575889fd9b726a710abff78e1ecc8427b668d5d
Signed-off-by: Wisley Chen <wisley.chen@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44631
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2020-09-11 15:49:18 +00:00
Rob Barnes 875d0c22b8 mb/google/zork: Add woomax memory ID 0
Woomax needs memory ID 0 to map to MT40A512M16TB-062E:J.

BUG=b:165611555
TEST=None

Signed-off-by: Rob Barnes <robbarnes@google.com>
Change-Id: Ibbcef6be382bd6649c93cfe92427f124dd137112
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45264
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-11 15:41:21 +00:00
Nikolai Vyssotski 1e633e88dd soc/amd/picasso: Fix TSC frequency calculation
Fix TSC frequency calculation per Picasso PPR. This code was copied
from Stoney and was incorrect for Picasso.

BUG=b:163423984
TEST=verify Dalboz TSC to be 1GHz
BRANCH=zork

Change-Id: Ibe3f49c7d295e7336ee042da2b94823171b6eb55
Signed-off-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45055
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2020-09-11 15:32:14 +00:00
Felix Held 1fa45b1460 vc/amd/fsp/picasso: Fix FSP-S UPD header file formatting
Use one tab instead of 8 spaces at the beginning of the lines added in
commit 39a8040ddc.

Change-Id: I8d7553e1b41dbbbdabd7392028a51e3a0f79c97a
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45257
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2020-09-11 14:28:38 +00:00
Felix Held b026c7c65a soc/amd/common/espi_util: clarify espi_open_io_window
Calling espi_open_generic_io_window in espi_open_io_window depends on
the condition in the preceding if statement, so move the command into an
else block to make it more obvious that this is the case.

TEST=Timeless build results in identical image.

Change-Id: I3039817afd79c30a2df2f2f54e7848f52dc2c487
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44353
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2020-09-11 14:27:57 +00:00
Subrata Banik 3999aa6cdb soc/intel/tigerlake: Clean up systemagent.h
List of changes:
1. Convert inconsistent white space into tab.
2. Group together all MCHBAR offset macros.

Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Change-Id: I82fc362589389081b1b1856524a972b780af9a13
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45256
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-11 03:14:05 +00:00
Subrata Banik 86e53267c4 device: Fix incompatible-pointer-types build error
The build error `incompatible-pointer-types` occurs while using
`pci_dev_request_bus_master` as part of device ops

Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Change-Id: I3b1ce85b8db1ddf9ac860415edbe64694b91b3d1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45122
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-11 03:13:17 +00:00
Alex Levin a903ea8d62 mb/google/volteer/variants/volteer2: route GPP_F14 via APIC
GPP_F14 should be configured to be routed via APIC and not SCI.

BUG=b:162528549
TEST=verified on a volteer2

Signed-off-by: Alex Levin <levinale@google.com>
Change-Id: I7f2c7af230dd75b3cb3806e2b186725d49da9e68
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45279
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-11 01:04:36 +00:00
Julius Werner 8678d47deb trogdor: Strappings_update_final3.1_second_thisistherealone.patch
Apparently what I thought was lazor-rev2 is actually lazor-rev3 and
nobody is really sure what lazor-rev4 is going to be at this point or
how we proceed from there. What seems to be somewhat agreed upon is that
for now all Lazor revisions use the "old" GPIO mapping and it's not very
clear if that's ever going to change for Lazor, so let's take the
revision restriction out from Lazor for now.

Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: I4939ccfd8464da6e72b5e01a58489b8c80f5b4df
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45225
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Douglas Anderson <dianders@chromium.org>
Reviewed-by: Philip Chen <philipchen@google.com>
2020-09-10 21:40:07 +00:00
Rob Barnes b2545cc3c6 soc/amd/picasso: Move APCB generation out of picasso
Move APCB generation out of the picasso makefile and into the mainboard
makefile. APCB generation tends to be mainboard specific and does not
belong in the soc makefile.

BUG=b:168099242
TEST=Build mandolin and check for APCB in coreboot binary
     Build and boot ezkinil

Change-Id: Ib85ad94e515f2ffad58aafe06c1f1d4043e9303c
Signed-off-by: Rob Barnes <robbarnes@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45222
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-10 20:26:03 +00:00
Michael Niewöhner 3992da034f lib/Makefile.inc: fix hex-to-bin conversion of SPD files
This fixes the hex-to-bin conversion command, used to generated binary
SPD files from hexdumps.

An issue that only appeared on one of my systems, where conversion of
'01 02 03' to binary resulted in \x01\x32\x03 instead of \x01\x02\x03:

for c in 01 02 03; do printf $(printf '\%o' 0x$c); done | xxd -g 1
00000000: 01 32 03                                         .2.

The reason for this was that the syntax in lib/Makefile.inc is wrong,
because the backslash must be escaped due to chaining two printf
commands.

Change-Id: I36b0efac81977e95d3cc4f189c3ae418379fe315
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45207
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-10 17:30:00 +00:00
Jason Glenesk f459a4084e soc/amd/picasso: Add MADT entry for GNB IOAPIC
Add the missing entry using new Kconfig symbol for IOAPIC ID. coreboot
will always enable the GNB IOAPIC.

Cq-Depend: chrome-internal:3247431, chrome-internal:3253044
BUG=b:167421913, b:166519072
TEST=Boot fully to morphius board with and without amd_iommu kernel
     parameter. Dump MADT and IVRS tables. Cross check ioapic entries
     in MADT against IVRS.
BRANCH=Zork

Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Signed-off-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com>
Change-Id: Ic4a2e9b71dba948e8a4907e5f97131426d8a4a3e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45056
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-10 12:38:19 +00:00
Marshall Dawson 39c64b0bdd soc/amd/picasso: Assign IOAPIC IDs, GNB APIC base with FSP
Add Kconfig symbols for the FCH and GNB IOAPIC IDs, then pass
the info to FSP to keep it in sync with coreboot.  Do the same
for the northbridge's IOAPIC base address.

Use the new values where needed, and reserve the resources
consumed by the GNB IOAPIC.

BUG=b:167421913, b:166519072
TEST=Boot Morphius and verify settings
BRANCH=Zork

Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Change-Id: I57d3d6b2ebd8b5d511dbcb4324ea065cc3111a2d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45115
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-10 12:37:45 +00:00
Marshall Dawson 39a8040ddc vc/amd/fsp/picasso: Sync FSP-S UPD header file
Sync the UPD definitions with the latest auto-generated files.
Definitions and usage will be updated in a subsequent FSP
Integration Guide.

Cq-Depend: chrome-internal:3247431
BUG=b:167421913, b:166519072, b:159664044
TEST=Boot morphius
BRANCH=Zork

Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Change-Id: Ic85e1f457c8932d933d8645738de68319dbf375a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45113
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2020-09-10 12:37:29 +00:00
Yu-Ping Wu aa78c9ea4a mb/google/asurada: Add config for hayato
BUG=b:163789704
TEST=emerge-asurada coreboot
BRANCH=none

Change-Id: I1a5928fb81356aaf040534e1675933a504aa9f95
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45163
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-10 06:39:45 +00:00
Elyes HAOUAS 1a8b50089d soc/mediatek: Drop unneeded empty lines
Change-Id: Ia419de14614a7a1b583e0870e9ca2fcdc8cf815a
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44596
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2020-09-10 06:37:52 +00:00
Maxim Polyakov f8f8615eef mb/siemens/mc_apl2/gpio: Fix code style
Use the 96 character limit for pad macros.

Change-Id: I03fd2f9309c04628c46e3473bed280edc57e215c
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44470
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
2020-09-10 05:35:11 +00:00
Maxim Polyakov e05aafbc67 mb/siemens/mc_apl2/gpio: Undo set DRIVER for GPO
GPIO Driver mode is used for configuration interrupt routing for
external devices through GPI. But there is no point in configuring
this for GPO. This patch replaces the PAD_CFG_GPO_GPIO_DRIVER macro
with others that do not set the corresponding bit in the Host Software
Pad Ownership register.

Change-Id: I406a08e526a6c655f38e4c0a355957c98e93881c
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44469
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
2020-09-10 05:34:49 +00:00
Subrata Banik 2ee4c0d7f4 vendorcode/intel/fsp/alderlake: Fix FSPS_ARCH_UPD redefinition issue
FSPS_ARCH_UPD struct is part of edk2-stable202005 branch (FspApi.h)
hence local definition of FSPS_ARCH_UPD inside FspsUpd.h is causing
compilation issue.

Change-Id: Id5b3637d9ab6d87aab6da810f9c83d3258900a29
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45191
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
2020-09-10 05:27:03 +00:00
Subrata Banik fed1a1a8b0 soc/intel/alderlake: Rename pch_init() code
Rename the pch_init function to bootblock_pch_init to
maintain the parity with previous generation SoC code block.

Refer to commit 1201696.

Change-Id: Id2a89b2f64b58079062d79e07efbdcfad7ed3d2d
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45189
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-10 05:26:46 +00:00
Subrata Banik 4df75dc498 soc/intel/tigerlake: Maintain consistent tab in iomap.h
This patch converts inconsistent white space into tab.

Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Change-Id: If5e191b92e3e53b43335136ef51bc62589b955a0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45194
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
2020-09-10 05:26:21 +00:00
Vinod Polimera 3b4c45efa2 sc7180: Add display hardware pipe line initialization
Add sc7180 display hardware pipeline programming support
and invoke the display initialization from soc_init.

Changes in V1:
- added display init required check.
- added edid read function using i2c communication.
- added sn65dsi86 bridge driver to init bridge.
- moved display initialization to mainboard file.

Changes in V2:
- moved diplay init sequence to mainboard file
- moved edid read function to bridge driver.
- calculated timing paramters using edid parameters.
- removed command mode config code.
- moved bridge driver to drivers/ti.
- seperated out bridge and soc code with mainboard file as interface.

Changes in V3:
- add GPIO selection at runtime based on boardid.
- add vbif register struct overlay.

Changes in V4:
- update gpio config for lazor board.

Change-Id: I7d5e3f1781c48759553243abeb3d694f76cd008e
Signed-off-by: Vinod Polimera <vpolimer@codeaurora.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39615
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2020-09-10 00:25:26 +00:00
Vinod Polimera c4e0b0a313 sc7180: Add support for sn65dsi86 bridge
Add sn65dsi86 bridge driver to enable the eDP bridge.
Datasheet used : https://www.ti.com/lit/ds/sllseh2b/sllseh2b.pdf

Changes in V1:
- fix the dp lanes using mask
- separate out the refclk and hpd config to init function

Change-Id: I36a68f3241f0ba316c261a73c2f6d30fe6c3ccdc
Signed-off-by: Vinod Polimera <vpolimer@codeaurora.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42899
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2020-09-10 00:24:42 +00:00
Vinod Polimera c6880b3e9d sc7180: Add display dsi interface programming
This change adds support for sc7180 dsi interface host programming.

Changes in V1:
- remove dual dsi config code.
- update register access using struct overlays.
- remove dsc config & command mode code.

Changes in V2:
- remove dsi read and write functions.
- remove target and panel related code.

Changes in V3:
- move prototypes to headers.
- define macros for constants.

Changes in V4:
- define register bits instead of hardcoded values.

Change-Id: Ie64354ce8bc2a64b891fb9478fbca38d6ec4c321
Signed-off-by: Vinod Polimera <vpolimer@codeaurora.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39614
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2020-09-10 00:22:50 +00:00
T Michael Turney 0b493bbb9e sc7180: enable bl31
Developer/Reviewer, be aware of this patch from Napali:
https://review.coreboot.org/c/coreboot/+/28014/44

Change-Id: Ia961ee0e30478e21fd786ce464655977449df510
Signed-off-by: Ashwin Kumar <ashk@codeaurora.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35504
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2020-09-10 00:22:39 +00:00
Angel Pons 43810cb179 soc/intel/common/block/imc: Drop unused code
Nothing uses this code anymore.

Change-Id: I5da1020597c126a40b015beb6e43fb0168aa330f
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45046
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Andrey Petrov <andrey.petrov@gmail.com>
2020-09-09 23:21:19 +00:00
Vinod Polimera 4cdd0979ca sc7180: Add display 10nm phy & pll programming support
Adds basic headers as well as source required for display
dsi 10nm phy & pll programming.

Changes in V1:
- add struct overlays to model hardware registers.
- remove typedef structures.
- remove dead code such as dual dsi,split config etc.

Changes in V2:
- remove panel related header files.
- update the bitclock calculation using edid parameters.
- add phy timing calculation function.
- update copyright license.

Changes in V3:
- update the mdss clock structure.
- remove dsi_phy_configinfo_type struct.
- remove unused struct fields.

Changes in V4:
- update clock apis.
- remove unused structures.

Change-Id: I8ff400922ae594f558cf73a5aaa433a3a93347c2
Signed-off-by: Vinod Polimera <vpolimer@codeaurora.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39613
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2020-09-09 22:09:09 +00:00
Taniya Das dc92cea680 sc7180: clock: Add display external clock in coreboot
Add support for display external clock in coreboot for SC7180.

Tested: Display clocks are configured.

Change-Id: Ida222890252b80db738fa1f685b212b3f7c6e689
Signed-off-by: Taniya Das <tdas@codeaurora.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39612
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2020-09-09 22:08:49 +00:00
Ashwin Kumar 6856ae468e trogdor: Change Memlayout to increase QcLib region from 512 to 596kB
Change-Id: I49008ea9bc6254c745352b2e8ee965ddc2e8e5e4
Signed-off-by: Ashwin Kumar <ashk@codeaurora.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36277
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2020-09-09 22:08:34 +00:00
vsujithk 32aed01c6a sc7180: GPIO: Add I2S configuration for google/trogdor
Configure GPIO pins as I2S mode for audio speaker.

The audio speaker does not work on Trogdor revision 1, as the
layout was changed.

Developer/Reviewer reference, be aware of this issue:
https://partnerissuetracker.corp.google.com/issues/146533652

Change-Id: Ia4bbfea591a3231640b53e64f0e4e9d43c4437a3
Signed-off-by: vsujithk <vsujithk@codeaurora.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41428
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2020-09-09 22:08:19 +00:00
ashk b05e540217 trogdor: SoC makefile blob support
Following blobs will includes with SoC makefile:
  * AOP
  * BOOT
  * QTISECLIB
  * QCSEC
  * QUPV3FW

Change-Id: I85a20ef31ec91c6f22221d16fd4c3097c5cb97d1
Signed-off-by: Ashwin Kumar <ashk@codeaurora.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35508
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2020-09-09 22:07:31 +00:00
David Wu 43e601312b mb/google/volteer/var/trondo: Add memory parts and generate DRAM IDs
Add memory parts and generate DRAM IDs for trondo.

BUG=None
TEST=FW_NAME=trondo emerge-volteer coreboot chromeos-bootimage

Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: I2e89ecaf73a30595ed48ac9ce94ccbd4bb7ed3c2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45164
Reviewed-by: Michael Niewöhner
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-09 14:58:07 +00:00
Johnny Lin d04c06b472 drivers/ipmi: Add CONFIG_IPMI_KCS_TIMEOUT_MS for IPMI KCS timeout value
With the current timeout of 1000 cycles of 100 microsecond would see
timeout occurs on OCP Delta Lake if the log level is set to values
smaller than 8. Because the prink(BIOS_SPEW, ..) in ipmi_kcs_status()
creates delay and avoid the problem, but after setting the log level
to 4 we see some timeout occurs.

The unit is millisecond and the default value is set to 5000 according
to IPMI spec v2.0 rev 1.1 Sec. 9.15, a five-second timeout or greater
is recommended.

Tested=On OCP Delta Lake, with log level 4 cannot observe timeout
occurs.

Change-Id: I42ede1d9200bb5d0dbb455d2ff66e2816f10e86b
Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45103
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-09 13:39:36 +00:00
nick_xr_chen 44097e21cc mb/google/volteer/variants/eldrid: add memory.c for ddr4 support
Add new memory.c to support DDR4 memory types.

Use the new meminit_ddr() and variant_memory_sku() for eldrid variant
code on memory.c

The initial settings override the baseboard from volteer and fine tune
gpio.c and overridetree.cb on eldrid's configuration.

BUG=b:161772961
TEST='emerge-volteer coreboot chromeos-bootimage' and verify that Eldrid
can boots. NOTE that tests the ddr4 side of the implementation.

Change-Id: I2c7b30093a8d85bac5aba5b83768af5eb36c4f70
Signed-off-by: Nick Chen <nick_xr_chen@wistron.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44632
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
2020-09-09 13:37:41 +00:00
Sam Lewis 266c136304 soc/ti/am335x: Fix MLO build
Allows the AM335X to boot from the coreboot generated MLO by:

- Fixing the load address in the MLO header to be the start of SRAM
- Fixing the way that the bootblock size is calculated (which is
  embedded into the MLO so that the MLO knows how much to load into
  SRAM). The previous method relied on parsing cbfstool output - the
  output has changed format since this was originally written so this no
  longer works. Directly using the filesize of the built binary is
  probably a more stable way of doing this.

As part of this, the start addresses of SRAM and DRAM were fixed to be
consistent with the AM335x Technical Reference Manual (spruh73, rev Q).

TEST: Booted Beaglebone Black from MLO placed at offset 0x00 on an SD card

Change-Id: I514d7cda65ddcbf27e78286dc6857c9e81ce6f9e
Signed-off-by: Sam Lewis <sam.vr.lewis@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44381
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-09 10:49:05 +00:00
Sam Lewis f58fb59ea0 mb/ti/beaglebone: Init UART in early init
The console is initialized before mainboard_init, so the peripheral
should be initialized in bootblock_mainboard_early_init rather than
bootblock_mainboard_init.

Change-Id: I9f4ba29798eb0b1efea76f5ade4a234fb35a2f83
Signed-off-by: Sam Lewis <sam.vr.lewis@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44380
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-09-09 10:48:56 +00:00
Angel Pons 3ecee09ebb soc/intel/common/block/uart/Kconfig: Drop unused symbols
They are not referenced anywhere.

Change-Id: Iff2d3b0063da5796e0bff1ada08b0a544c3f9a5a
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45049
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2020-09-09 10:47:21 +00:00
Rob Barnes ad1da3a326 util/spd_tools: Support comments in mem_parts_used
Allow comments prefixed with '#' in mem_parts_used csv file.

BUG=None
TEST=Run gen_part_id with mem_parts_used file containing comments

Change-Id: Ia9e274d45aa06dea7a3a5f8cd1c8ee2b23398876
Signed-off-by: Rob Barnes <robbarnes@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44950
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-09-09 10:46:03 +00:00
Angel Pons eeb4705fff soc/intel/xeon_sp: Select CPU_INTEL_COMMON
This is an intermediate step to have SOC_INTEL_COMMON_BLOCK_CPU select
CPU_INTEL_COMMON directly, to avoid dependency problems.

Tested with BUILD_TIMELESS=1: Without including the config file in the
coreboot.rom, both OCP Tioga Pass and Delta Lake remain identical.

Change-Id: I565e75869be730e7c2fe7114b829941bc9890e6c
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45041
Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-09 10:40:40 +00:00