2 commits

Author	SHA1	Message	Date
Subrata Banik	65f5932e0c	soc/intel/alderlake: Add SPI DMI Destination ID ... Port commit 237afda (src/soc/intel/tigerlake: Add SPI DMI Destination ID) into Alderlake. Change-Id: Ia0b465d405ab3c70b7d4094d32c182cab30fe531 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48754 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>	2020-12-23 03:28:47 +00:00
Subrata Banik	2871e0e78c	soc/intel/alderlake/ramstage: Do initial SoC commit till ramstage ... List of changes: 1. Add required SoC programming till ramstage 2. Include only required headers into include/soc 3. Add CPU, PCH and SA EDS document number and chapter number 4. Fill required FSP-S UPD to call FSP-S API Change-Id: I3394f585d66b14ece67cde9e45ffa1177406f35f Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45759 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>	2020-10-03 12:15:22 +00:00