Commit Graph

17392 Commits

Author SHA1 Message Date
Hannah Williams 01bc897dfa soc/apollolake: Add helper functions to access Power Management Registers
Change-Id: I928efea33030e03cbbaead6812c617d20446f7c9
Signed-off-by: Hannah Williams <hannah.williams@intel.com>
Reviewed-on: https://review.coreboot.org/14289
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
2016-04-15 16:23:55 +02:00
York Yang 9c6c791351 mainboard/intel: Add Broadwell-DE based Camelback Mountain CRB
Initial files to support Camelback Mountain CRB. This board uses
Broadwell-DE code which is based on FSP 1.0. Change is based on
Broadwell-DE Gold release.

Windows 7 and Fedora 21 have been verified using SeaBIOS payload,
also Fedora 21 with U-Boot payload.

Change-Id: Ie249588b79430084adeebbcdd8b483d936c655e3
Signed-off-by: York Yang <york.yang@intel.com>
Reviewed-on: https://review.coreboot.org/14015
Tested-by: build bot (Jenkins)
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2016-04-15 16:21:36 +02:00
Patrick Georgi c42b786485 stddef.h: fix zeroptr's definition
As Aaron pointed out, the old definition made the compiler emit two
memory accesses, to 0 (for derefencing) and then reading at whatever
address could be read from there.

Change-Id: I5cdd53f5bd2d2397c43f09f3e5fa46be08744b01
Found-by: Aaron Durbin <adurbin@chromium.org>
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://review.coreboot.org/14342
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-04-15 16:18:57 +02:00
Furquan Shaikh b3ee03c404 bootblock_crt0: Use CR* macros from cpu/x86/cr.h
Instead of re-defining the macros, include cpu/x86/cr.h in
bootblock_crt0.S to re-use already defined macros for accessing CR*
flags.

Change-Id: Idade02f7a6bc880c9aad3bfacd05ac57b6d04e44
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/14359
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
2016-04-15 01:31:16 +02:00
Zhao, Lijian 44d009dc7f soc/intel/apollolake: Fix northbridge _CRS
Fix build break on current _CRS method with correct scope.

Change-Id: I75ba8abc547ec69be0a0950e23a7c31b447af31e
Signed-off-by: Zhao, Lijian <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/14288
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-04-15 00:25:06 +02:00
Martin Roth a29bc9786d Makefile.inc: Disassemble the ACPI AML to detect errors
This should help catch cases where the AML is not correct.

Change-Id: I48efb9ed0b62b3e17dcf3045ef9c32d813a412bc
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/14340
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-04-14 20:20:41 +02:00
Timothy Pearson 7f53b98112 mb/asus/kgpe-d16|kcma-d8: Do not assign IRQ to LPC HW monitor
On specific revisions of the ASUS KGPE-D16 (> 1.03G) there is a
high (< 1:10) chance of lockup from spurious HW monitor IRQs
during LPC configuration.  This was originally erroneously identified
as a bug within the SP5100 southbridge due to serial console buffering
moving the hang slightly before HW monitor setup.  It is currently
unknown how changing the CBFS layout / code size was able to alter
the frequency of the lockup occuring; this odd characteristic made
debugging extremely difficult, and it also indicates testing
across multiple PCB revisions will be neded to verify that the
bug has been completely resolved.

It is highly likely that the KCMA-D8 is also affected.  As there
does not seem to be a reason to keep the HW monitor IRQ enabled,
simply disable it on both mainboards.

This configuration has passed burn-on power cycle testing with
no lockups noted.  All other tests noted a lockup in under 25
power cycles or so, with failure typically occuring in under 5
power cycles; the affected Rev. 1.04 KGPE-D16 has cycled 25 times
times using this patch with only one failure finally noted.  This
final failure may have in fact been related to SP5100 Erratum 18
as the frequency is more in line with the errata document guidelines.

Change-Id: Ie9f4f37d2c7dfad0a02daff8b75cd2a1e6f1b09a
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/14333
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
2016-04-14 19:49:25 +02:00
Marcel Meißner cb672a5857 libpayload: Enable USB support by default
Most people use USB keyboards.

Change-Id: Ia7cf513059565db7b86190c4aae62d7a35392408
Signed-off-by: Marcel Meißner <mm-meissner@gmx.de>
Reviewed-on: https://review.coreboot.org/7540
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-04-14 19:48:16 +02:00
Hannah Williams 2859c45033 intel/apollolake_rvp: Add sleepstates.asl to dsdt
cat /sys/power/state should show supported sleep states as freeze and 
mem where freeze is "Suspend to Idle" and mem is "Suspend to RAM"

Change-Id: Ia72aaf6642dcdc9106c1992af3cf6cb21a8fff4a
Signed-off-by: Hannah Williams <hannah.williams@intel.com>
Reviewed-on: https://review.coreboot.org/14285
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-04-14 19:29:28 +02:00
Hannah Williams 4e63077d6b soc/apollolake: Add ACPI platform sleep capability
Change-Id: I6854f410b4d3847238f0253b7fbb9bbe8f9da395
Signed-off-by: Hannah Williams <hannah.williams@intel.com>
Reviewed-on: https://review.coreboot.org/14282
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-04-14 19:29:04 +02:00
Paul Menzel 534c5e1133 util/xcompile/xcompile: Remove -Wno-unused-but-set-variable from CFLAGS
Do not disable warnings about unused but set variables to further
improve the code quality.

Change-Id: I25fa29ac42c9d09596d03f11fb01f31635a62a11
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://review.coreboot.org/3981
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
2016-04-14 19:15:21 +02:00
Jonathan Neuschäfer 0a20c08d0f romcc: Remove old test infrastructure, rework Makefile
Changes in visible behaviour:
 - The default make target doesn't run the tests anymore
 - All generated files are stored under util/romcc/build/
   (or $BUILD_DIR)

Change-Id: If003240742eb1902a6e9b337cdee299d7d66ee06
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/14341
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-04-14 19:13:07 +02:00
York Yang d7cba288e4 soc/intel: Add Broadwell-DE SoC support
Initial files to support Broadwell-DE SoC. This is FSP 1.0 based
project and is based on Broadwell-DE Gold release. Change has been
verified on Intel Camelback Mountain CRB.

Change-Id: I20ce8ee8dd1113a7a20a96910292697421f1ca57
Signed-off-by: York Yang <york.yang@intel.com>
Reviewed-on: https://review.coreboot.org/14014
Tested-by: build bot (Jenkins)
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Martin Roth <martinroth@google.com>
2016-04-14 19:02:07 +02:00
Martin Roth cd9aec6fb0 util/lint: Update lint-stable-000-license-headers
Add all currently clean directories.

Change-Id: Ibfb6432b485adb7fdc930f57ea0af4ff35921d37
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/14332
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-04-14 17:46:48 +02:00
Martin Roth ae10016c8b mainboard/intel/apollolake_rvp: Update license headers
Update all of the license headers to make sure they are compliant
with coreboot's license header policy.

Change-Id: Ia78cf5a4b283b846346e5e50c6b2b36299a6a892
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/14363
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-04-14 17:45:27 +02:00
Martin Roth 62d3400dd9 src/soc/rockchip: Update license headers
Update all of the license headers to make sure they are compliant
with coreboot's license header policy.

Change-Id: Iea1a4b8f7df08d2ae694401211b0b664f5980b02
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/14327
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-04-14 16:54:49 +02:00
Martin Roth ebabfadcec soc/intel: Update license headers
Update all of the license headers to make sure they are compliant
with coreboot's license header policy.

Change-Id: I151d058615290e528d9d1738c17804f6b9cc8dce
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/14321
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-04-14 16:54:33 +02:00
Martin Roth a2f4758900 superio/smsc/mec1308: Fix AddressMax value for SMBX mailbox
The way this was implemented before was causing ACPI failures.  There
was also a basic misunderstanding of what the AddressMax field was used
for.  In this case, because it's a fixed address, it should be the same
as the AddressMin field.

Getting rid of the addition in the field solves the ACPI output problem.

Change-Id: Idec2bf0ed27ae694e98f141087cdf22401937178
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/14343
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Idwer Vollering <vidwer@gmail.com>
Reviewed-by: Duncan Laurie <dlaurie@google.com>
2016-04-13 23:39:28 +02:00
Vadim Bendebury fbec1ad4ef rockchip/common: do not retrieve register pointer twice
The driver interface function derives the driver specific pointer from
the API provided handle, no need to use the handle in the local
functions.

BRANCH=none
BUG=none
TEST=SPI interface with the flash ROM is still working properly.

Change-Id: I7725b658365473c733698ca050e780d1dd5072d9
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: a2b42779785623bd1234ab2dfb0b4db76c890fc7
Original-Change-Id: I9d657dc23540e9eac52d2dbfc551ed32b7fa98f0
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/338090
Original-Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://review.coreboot.org/14318
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
2016-04-13 23:39:16 +02:00
Lin Huang 6d6b129ea4 rockchip/rk3288: refactor pwm driver
3288 and 3399 use the same pwm controller.

With this patch in place it is easy to add support for 3399.

BRANCH=none
BUG=none
TEST=booted veyron_jerry to kernel login prompt

Change-Id: If8f5697b4003d078b46de3fa3cebad6c8310a688
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: acf6132619167743c0c991b75f0f49c8d0e51ca7
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Change-Id: I79428f9ec71017ad8f3ad67dac1468178ccc3a1e
Original-Reviewed-on: https://chromium-review.googlesource.com/338019
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/14336
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-04-13 23:38:50 +02:00
huang lin d4c175b97b rockchip/rk3288: refactor i2c interface to allow support of rk3399
Both SOCs use the same base i2c controller, the difference mostly
being the number of interfaces and distribution of the interfaces'
registers between register files.

Upload check was complaining about misspelled labels, fixed them to
pacify the check.

With this patch in place it is easy to add support for 3399.

BUG=none
BRANCH=none
TEST=brought up veyron_mickey all the way to booting the kernel. It
     properly recognized the TPM and the edid of the panel, proving
     that i2c interface is operational.

Change-Id: I656640feabd0fc01d2c3b98bc5bd1e5f76f063f6
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 82832dfd4948ce9a5034ea8ec0463ab82f0f5754
Original-Change-Id: I4829ea53e5f4cb055793d9a7c9957d6438138956
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/337971
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/14335
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-04-13 23:38:31 +02:00
huang lin c14b54dd17 rockchip/rk3399: Add a stub implementation of the rk3399 SOC
Most things still need to be filled in, but this will allow
us to build boards which use this SOC.

BRANCH=none
BUG=chrome-os-partner:51537
TEST=with the rest of the patches applied Kevin board can be booted to
     Linux login propmt.

Change-Id: I6f2407ff578dcd3d0daed86dd03d8f5f4edcac53
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 27dfc39efe95025be2271e2e00e9df93b7907840
Original-Change-Id: I6f2407ff578dcd3d0daed86dd03d8f5f4edcac53
Original-Signed-off-by: huang lin <hl@rock-chips.com>
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/332385
Reviewed-on: https://review.coreboot.org/13915
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-04-13 23:37:55 +02:00
Edward O'Callaghan 46f8bd70ef amd/agesa/family12/dimmSpd.c: Indent (tab) fix
Trivial; Use tab over space for indent. Clean up some ASCII art
while here.

Change-Id: Id2478d140a98596c5eeefdf5b047c1ca23203909
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: https://review.coreboot.org/8016
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-04-13 21:16:18 +02:00
Nicolas Reinecke 2bffa8aa84 lenovo/t420: Add new port
This is based on t420s. Tested on a T420 without discrete GPU.
There is no support for nvidia gpu and optimus.

Signed-off-by: Nicolas Reinecke <nr@das-labor.org>
Tested-by: Iru Cai <mytbk920423@gmail.com>
Change-Id: Ie9405966e56180ac1c43a3c5b83181ee500177c8
Reviewed-on: https://review.coreboot.org/11765
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-04-13 17:54:46 +02:00
Martin Roth 888a98b872 payloads: add iPXE 'payload' build
We already have the ability to add a pxe rom to cbfs, but it needs to be
configured and built separately.

This moves the existing Kconfig options for PXE from device/Kconfig and
the top level Makefile.inc to payloads, and adds the option to download
and build iPXE as part of the coreboot build process.

This configures the serial output of iPXE to match coreboot's serial
port configuration by editing the .h files. iPXE doesn't give any
real build-time method of setting these configuration options.

Change-Id: I3d77b2c6845b7f5f644440f6910c3b4533a0d415
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/14085
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-04-13 17:45:37 +02:00
Martin Roth 84129b8c68 util/lint: update lint-000-license-headers
- Add some additional filters for files that do not require
license headers.
- Add an alternative wording for the BSD license that is used
in several files.
- Add string for dummy files
- Stop checking if there are no files left.
- Remove 'local' keyword which is not posix compliant.

Change-Id: I2ed1b0572b5fbe84ea86173b7ec2106454399547
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/14324
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-04-13 17:37:53 +02:00
Jonathan Neuschäfer e69d6c2e7b romcc: Rewrite the test system
Differences:
 - The test logic is now only implemented in one place (pending the
   deletion of the old parts), whereas it previously was implemented
   both as make rules and as a pair of shell scripts.
 - Tests don't need to be registered anymore. Just adding a new file
   with the correct name is enough to have it tested.
 - The code is hopefully more readable and maintainable.
 - The new test script supports colors (if the standard output is a
   terminal and --nocolor was not passed on the command line).

Things to do in follow-up patches:
 - Remove the old test code
 - Test or remove fail_test*.c, hello_world*.c and raminit_test*.c
 - Fix regressions that have built up over the years, while making sure
   not to introduce new ones
 - Makefile integration
 - Jenkins integration

There are tests in the makefile that specify -fno-always-inline, but
this option doesn't exist anymore, so I didn't port them over.

Change-Id: Idd6b89368c1e36555cb880c37bbe07035c938cd7
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/14291
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins)
2016-04-13 17:37:28 +02:00
Jonathan Neuschäfer 3cfbc4a608 romcc: Use UNIX line endings in linux tests
This makes it easier to check the output against a reference output.

Change-Id: I9c7ae538b708399a5cadd18e498618d7480d240f
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/14276
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
2016-04-13 17:37:03 +02:00
Jonathan Neuschäfer 9551cf4709 romcc: Increase base address in linux ld script
Newer versions of Linux implement a sysctl variable called vm.mmap_min_addr
that controls the minimum address a virtual memory mapping may have[1]. It is
usually set to 64KiB.

Map the start of the segment specified in util/romcc/tests/ldscript.ld to
128KiB, just to be sure.

[1]: https://www.kernel.org/doc/Documentation/sysctl/vm.txt

Change-Id: I72a5c65ca5e7d3a77d6ec897ae3287e3ea05cc2f
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/14277
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
2016-04-13 17:36:39 +02:00
Martin Roth c5b0e3b566 southbridge/via: Update license headers
Update all of the license headers to make sure they are compliant
with coreboot's license header policy.

Change-Id: Id6d11d1cea3ebde4adf63e3d98ac603d85591d5b
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/14331
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-04-13 17:36:14 +02:00
Martin Roth 3aa362bca9 southbridge/ti: Update license headers
Update all of the license headers to make sure they are compliant
with coreboot's license header policy.

Change-Id: I61938b42c5aa75d1c7706a1c5ae45dace6704c86
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/14330
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-04-13 17:36:00 +02:00
Martin Roth 411ca3d663 southbridge/ricoh: Update license headers
Update all of the license headers to make sure they are compliant
with coreboot's license header policy.

Change-Id: I9689bf4ccc5f639bd98d6277bdd27afe4bb4295b
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/14329
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-04-13 17:35:43 +02:00
Martin Roth 9943b8829b southbridge/nvidia: Update license headers
Update all of the license headers to make sure they are compliant
with coreboot's license header policy.

Change-Id: I7a19ed8cf16b9424190800940d2b8ec1a96c5ce9
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/14328
Reviewed-by: Myles Watson <mylesgw@gmail.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-04-13 17:35:29 +02:00
Martin Roth 87f025aa21 src/soc/marvell: Update license headers
Update all of the license headers to make sure they are compliant
with coreboot's license header policy.

Change-Id: I4572eec52bf834e4fac7bc5b54ceb591a0173a69
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/14326
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-04-13 17:34:33 +02:00
Martin Roth bb5953d1d0 src/device: Update license headers
Update all of the license headers to make sure they are compliant
with coreboot's license header policy.

Change-Id: I5e5180ec4303a121609b4acffb284daea6b08379
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/14325
Reviewed-by: Myles Watson <mylesgw@gmail.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-04-13 17:34:18 +02:00
Martin Roth 31a477c3e8 mainboard/google: Update license headers
Update all of the license headers to make sure they are compliant
with coreboot's license header policy.

Change-Id: Ied67c5079a7f49594edb39caf61fe7f386c3f80d
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/14323
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-04-13 17:34:04 +02:00
Martin Roth ac0478150e mainboard/intel: Update license headers
Update all of the license headers to make sure they are compliant
with coreboot's license header policy.

Change-Id: I260c1ae8d0f7306dd0c72c9ca05f0789cd915a61
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/14322
Tested-by: build bot (Jenkins)
Reviewed-by: Damien Zammit <damien@zamaudio.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-04-13 17:31:12 +02:00
Patrick Rudolph eaa57736ac device/pci_rom: Always use pci_rom
The following series always needs to access the functions
provided pci_rom.c.

Remove the dependency to CONFIG_VGA_ROM_RUN and depend on
CONFIG_PCI instead.

Change-Id: I6ed7ff5380edc7cd88dc1c71b43b1129a3de0f52
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/14219
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-04-13 17:21:07 +02:00
Damien Zammit 711a478c05 intelmetool: Fix detection logic of no MEI device
Previously, on systems that are supposed to have ME but
are librebooted, there was no message printed to tell the user
that no MEI was detected.  Fixed this bug.

Change-Id: I59681c194ae5e76533dd777374e26d1aea727337
Signed-off-by: Damien Zammit <damien@zamaudio.com>
Reviewed-on: https://review.coreboot.org/14334
Tested-by: build bot (Jenkins)
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@googlemail.com>
2016-04-13 17:20:36 +02:00
Andrey Petrov c6ee58c790 soc/intel/apollolake: Add tsc_freq.c to all the stages
Change-Id: I3120a52e21cf4ad03bb1d16b5b2b8a5e68aabf3f
Signed-off-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-on: https://review.coreboot.org/14339
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
2016-04-13 16:08:47 +02:00
Bora Guvendik 399332d271 soc/intel/apollolake: Enable TPM in bootblock stage
Configure gpio FST_SPI_CS2_N before verstage so that tpm can be
accessed.

Change-Id: I238bf1cd508880b686f0625f28175a80de450971
Signed-off-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-on: https://review.coreboot.org/14254
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
2016-04-13 16:08:38 +02:00
Andrey Petrov e07e13d7fd soc/intel/apollolake: Update platform-specific FSP headers
This updates FSP UPD headers that adds new fields. Importantly
there are new FSPS UPD fields that allow to specify some BARs.
They are needed by FSP SiliconInit API to work properly.

Change-Id: Ie268c57c66b4d8fd6e00835916004058ff05762e
Signed-off-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-on: https://review.coreboot.org/14217
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
2016-04-13 16:08:25 +02:00
Andrey Petrov 28c78abaf7 soc/intel/apollolake: Reserve IMRs (Isolated Memory Regions)
Certain security features on the platform use IMRs. Unfortunately
this memory is unusable for OS or firware. This patch marks IMR
regions as unusable.

Change-Id: I4803c41c699a9cb3349de2b7e0910a0a37cf8e59
Signed-off-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-on: https://review.coreboot.org/14245
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
2016-04-13 16:08:09 +02:00
Aaron Durbin 108cd0e16d soc/intel/apollolake: logically group PMC BAR programming
The ACPI base address was being programmed sepearately from
the other BARs in the PMC device. Group all the programming
together so there isn't separate paths for programming the
relevant BARs.

Change-Id: Ib17684397fc19c42b39d066f981c01a886d65235
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/14320
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
2016-04-13 16:07:51 +02:00
Lee Leahy ff7670915c src/soc/intel/common: Fix CID 1295499, remove dead code
Restructure the nvm_is_write_protected routine to eliminate the dead
code error.

TEST=Build and run on Kunimitsu

Change-Id: Ia9170e27d4be3a34760555c48c1635c16f06e6a3
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/14337
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
2016-04-13 07:00:27 +02:00
Martin Roth e03305358f lint/lint-stable-004-style-labels: Update script
- Look at entire tree instead of just the current commit.  This was
causing the test to overlook some issues that were already in the tree.
- If git is on the system, and the code is in a git repo, use the
'git ls-files' command to find the files to examine.  If those
conditions aren't met, fall back to using the find command.
- Wrap the command so it's easier to read.

Change-Id: I3dce219a29ffb1ae56a31318b995e3ba8ea43e70
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/14194
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-04-13 02:11:28 +02:00
Patrick Rudolph 6c1e81059d MAINTAINERS: add myself
Add myself to MAINTAINERS file.

Change-Id: I959ef193b69095b05ae9e42bd10d3b21001e0bc8
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/14262
Tested-by: build bot (Jenkins)
Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
2016-04-13 02:01:38 +02:00
Martin Roth 444ece2a38 crossgcc: skip TARGETARCH for tools that don't use it
Many of the tools and libraries don't use a target architecture, but
they were still getting put in one. This change separates out the
builds that need the target architecture from the ones that don't,
and sets the build directory accordingly.

This will help keep from rebuilding the libraries when building all
of the tools if you keep the temporary files around (-t option).

Change-Id: Id6c17719332f2244657f103f5f07ca7812d51af1
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/14229
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-04-12 06:33:25 +02:00
Timothy Pearson c13866fd40 sb/amd/sp5100: Apply Sx State Settings per RPR v3.02
Change-Id: Iacf84ac7de4362e523ad9d8aa7309eecd5277480
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/14308
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
2016-04-11 23:25:23 +02:00
Timothy Pearson d1b6ff80c0 sb/amd/sp5100: Enable CPU reset timing option per RPR v3.02
Change-Id: Ifb568ca126283e533232f52175d6147ee500220c
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/14307
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins)
2016-04-11 23:25:04 +02:00