Commit Graph

31456 Commits

Author SHA1 Message Date
Kyösti Mälkki cc5193604f cpu/ti/am335x: Extend monotonic timer to early stages
It is actually all completely broken, dmtimer.c is
not really implemented.

Change-Id: Ifb3f624930c9ef663fae30cd5ddcb1d3d46f06b1
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36593
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2019-11-05 13:41:37 +00:00
Arthur Heymans acc88f8e66 drivers/intel/fsp2_0: Hide CONFIG_FSP_CAR
CONFIG_FSP_CAR should not be a user visible option, but depends on the
choice presented in the soc Kconfig.

This also removes the dependencies on ADD_FSP_BINARIES. You need to
included those for other stages too so there is no need to make this
requirement explicit for FSP-T.

Change-Id: Ida32e9c4f5839aef4d4deb7a1c7fabe6335a5d2a
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36169
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-11-05 09:49:08 +00:00
Arthur Heymans 127b820d24 soc/intel/common: Don't link CAR teardown in romstage
This is done in postcar stage. This also assumes CAR tear down will
always be done in postcar stage.

Change-Id: I0ff1624c20b9649ca0a8fa31c342bf99530076d7
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36166
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2019-11-05 09:40:44 +00:00
Peichao Wang 1e07d40027 mb/google/kahlee/treeya: Update STAPM parameters for Treeya
Tune stapm percentage from 80 to 68 and time from 250 second
to 90 second make them meet Lenovo temperature spec.

BUG=b:143859022
TEST=build firmware and install it to DUT and run fishbowl 1000,
check temperature whether meets spec.

Signed-off-by: Peichao Wang <peichao.wang@bitland.corp-partner.google.com>
Change-Id: I254140c9d242ed918b3b689d4fb4a1d0e871cd55
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35042
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Martin Roth <martinroth@google.com>
2019-11-05 03:09:19 +00:00
Maxim Polyakov 3a28673293 mb/asrock/h110m/devicetree: fix VR config info
Removes unnecessary information about the Ring Sliced VR configuration
from another board with FSP1.1 (which is no longer supported).

Change-Id: Ia2b90d9ede782852c2127da972333bada378b217
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36378
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2019-11-04 22:09:46 +00:00
Maxim Polyakov 0dd8fe7ec3 superio/nuvoton/nct5539d: use SuperIO ACPI generator
Adds SuperIO SSDT ACPI generator[1] support.
Not tested on real hardware.

[1] https://review.coreboot.org/c/coreboot/+/33033

Change-Id: If9fd56efd40ee0f860e206882418c8bdc7c16802
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36380
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2019-11-04 22:08:13 +00:00
Maxim Polyakov c4f77d943a mb/asrock/h110m: use SSDT generator for SuperIO
Modifies the device tree to use the ACPI SSDT generator[1] for NCT6791D
SuperIO, dropping the need to include code from the superio.asl, which
was inherited from another chip (NCT6776) and required fixes. SSDT gen
support for Nuvoton NCT6791D chip was added in the previous patch [2].

[1] https://review.coreboot.org/c/coreboot/+/33033
[2] https://review.coreboot.org/c/coreboot/+/36379

Change-Id: I57b67d10968e5e035536bcb0d8329ce09d50194b
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36381
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2019-11-04 22:07:05 +00:00
Maxim Polyakov facbf47224 superio/nuvoton/nct6791d: use SuperIO ACPI generator
Adds SuperIO SSDT ACPI generator[1] support.
It has been tested on Asrock H110M DVS motherboard [2].

[1] https://review.coreboot.org/c/coreboot/+/33033
[2] https://review.coreboot.org/c/coreboot/+/36381

Change-Id: Idad66546168bbd26f0a4241deb66e5bfd83367af
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36379
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2019-11-04 22:06:13 +00:00
Matt DeVillier 2449895709 google/auron: hook up libgfxinit
Internal/external displays functional on all variants
other than Samus. Unable to verify external outputs on
Samus (USB-C using DP/HDMI adapter).

Test: build/boot lulu variant with libgfxinit, verify internal/
external displays functional prior to OS display driver loaded.
Both linear framebuffer and scaled VGA text modes functional.

Change-Id: I867b2604861ebae02936e7fc0e7230a6adcb2d20
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36107
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-11-04 19:43:44 +00:00
Michael Niewöhner 7736bfc443 soc/intel/sgx: convert SGX and PRMRR devicetree options to Kconfig
The devicetree is not made for user-choosable options, thus introduce
Kconfig options for both SGX and the corresponding PRMRR size.

The PRMRR size Kconfig has been implemented as a maximum value. At
runtime the final PRMRR size gets selected by checking the supported
values in MSR_PRMRR_VALID_CONFIG and trying to select the value nearest
to the chosen one.

When "Maximum" is chosen, the highest possibly value from the MSR gets
used. When a too strict limit is set, coreboot will die, printing an
error message.

Tested successfully on X11SSM-F

Change-Id: I5f08e85898304bba6680075ca5d6bce26aef9a4d
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35799
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-11-04 19:25:02 +00:00
Michael Niewöhner e75a64f822 soc/intel: skl,cnl,icl: consolidate ebda and memmap
As of CB:36136 ebda and memmap are identical for skl, cnl and icl, thus
move them to common code.

Tested successfully on X11SSM-F

Change-Id: I9a20c814d2a6874fcb4ff99ef1a7825d891f74e2
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36137
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-04 19:24:49 +00:00
Michael Niewöhner 68da45479f soc/intel: skl,cnl,icl: rely on TOLUM as cbmem_top returned by FSP
Instead of doing our own calculations, rely on TOLUM returned by FSP
for cbmem_top. This (hopefully) saves us from making mistakes in weird
calculations of offsets and alignments.

Further this makes it easier to implement e.g. SGX PRMRR size selection
via Kconfig as we do not have to make any assumptions about alignments
but can simply pass (valid) values to FSP.

Tested successfully on X11SSM-F

Change-Id: If66a00d1320917bc68afb32c19db0e24c6732812
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36136
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-04 19:10:08 +00:00
Elyes HAOUAS 1644e48985 sb/intel: Use defined CONFIG_HPET_ADDRESS
Change-Id: I15ae5e70ba351e89d5ea9d04dbb1efdfbb372bba
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36458
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-11-04 13:19:42 +00:00
Elyes HAOUAS 4ec67fc82c nb/intel: Use defined DEFAULT_RCBA
Change-Id: I166dd3edb50699dfca7b60b83cfcae996ced90dc
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36464
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-11-04 13:13:13 +00:00
Patrick Rudolph 728a06032d soc/intel: Remove unused code
Delete acpi_create_intel_hpet() which has been replaced
by acpi_write_hpet() in the corresponding soc folders
some time ago.

Change-Id: I788c9ef27cdc575eb8467cbef64ee52f4053e197
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35207
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Guckian
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-11-04 12:00:11 +00:00
Patrick Rudolph b1ef725f39 cpu/qemu-x86: Add x86_64 bootblock support
Add support for x86_64 bootblock on qemu.

Introduce a new approach to long mode support. The previous patch set
generated page tables at runtime and placed them in heap. The new
approach places the page tables in memory mapped ROM.

Introduce a new tool called pgtblgen that creates x86 long mode compatible
page tables and writes those to a file. The file is included into the CBFS
and placed at a predefined offset.

Add assembly code to load the page tables, based on a Kconfig symbol and
enter long in bootblock.

The code can be easily ported to real hardware bootblock.

Tested on qemu q35.

Change-Id: Iec92c6cea464c97c18a0811e2e91bc22133ace42
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35680
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-11-04 11:58:58 +00:00
Elyes HAOUAS 6f7c955464 nb/intel/nehalem: Fix 'dead assignment'
Dead increment spotted out using clang-tools.
Value stored to 'some_delay_3_halfcycles' is never read.

Change-Id: I8133f9e8786006bd278d281a132b6a2bd863a967
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36135
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-11-04 11:57:06 +00:00
Marty E. Plummer 20994a763b cbfs: read header offset as explicitly LE
le32_to_cpu spits out uint32_t on BE targets, cast it.

Change-Id: Idc99b0c133faa2aa15d06f998e7371d332ffa490
Signed-off-by: Marty E. Plummer <hanetzer@startmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36346
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-11-04 11:56:04 +00:00
Jamie Chen ce6f1a53e9 mb/google/hatch: update DLL values for Kindred
Update emmc DLL values for Kindred

BUG=b:131401116
BRANCH=none
TEST=Boot to OS 100 times on Kindred EVT

Change-Id: Ibd840b31bb0e5a742495758de55b532e6c3946aa
Signed-off-by: Jamie Chen <jamie.chen@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36076
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Shelley Chen <shchen@google.com>
2019-11-04 11:55:24 +00:00
Arthur Heymans 9c0afe6e6b soc/intel/broadwell: Use sb/intel/common/acpi/platform.asl
Change-Id: I6d8d04289254317af8d7cc55c89431d408414384
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36583
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-11-04 11:48:34 +00:00
Arthur Heymans b9b79d2589 mb/*/*/others: Use sb/intel/common/acpi/platform.asl
Change-Id: Iabfd680fdb50534e6b9f6cfdecda9f8de0f8a610
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36582
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-11-04 11:48:19 +00:00
Arthur Heymans cf819ea654 soc/intel/{braswell,baytrail}: Use sb/common/intel/platform.asl
Change-Id: I64a27cb080838c986a12a40c80d0c91824b9d04c
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36581
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-11-04 11:47:13 +00:00
Arthur Heymans 72c483a95a sb/intel/lynxpoint: Use sb/intel/common/platform.asl
Change-Id: I86260a374a3f60f16dc73573e7989f0a4ffec818
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36580
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-11-04 11:46:42 +00:00
Arthur Heymans 2f9a0cdfa6 mb/*/*{i82801gx}: Use sb/intel/common/acpi/platform.asl
Change-Id: Ifc0799d26394a525d764fb4ffc096b48060ee22f
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36579
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-11-04 11:45:58 +00:00
Yu-Ping Wu 816326576a include: Remove EC_EVENT_* from elog.h
All of the EC_EVENT_* macros can be replaced with the EC_HOST_EVENT_*
macros defined in ec_commands.h, which is synchronized from Chromium OS
ec repository.

BRANCH=none
BUG=none
TEST=emerge-kukui coreboot

Change-Id: I12c7101866d8365b87a6483a160187cc9526010a
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36499
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2019-11-04 11:43:49 +00:00
Michael Niewöhner ab0d687fc5 mb/supermicro/x11-lga1151-series: drop console guard in bootblock
To make debugging possible in a fallback setup, the serial console must
be set up in bootblock, thus drop the guard.

Change-Id: If0dd3c03ba52b4936eb234e6b2b61bb5ce044fcd
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36602
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-04 11:43:10 +00:00
Michael Niewöhner 403b70adb9 mb/supermicro/x11-lga1151-series: use new console delay Kconfig option
This replaces the hardcoded delay by the new Kconfig option.

Change-Id: I8bf4ef7ad9beea7b3dc22e1567623a423597eff9
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36592
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-11-04 11:42:42 +00:00
Michael Niewöhner 4d877c8c7f superio/aspeed/common: add workaround for serial routing delay quirk
Some mainboards with an ASPEED BMC do the serial routing setup in the
BMC boot phase on cold boot. This results in scrambled console output
when this is not finished fast enough.

This adds a delay of 500ms as workaround in the BMCs uart setup that
can be selected at mainboard level.

A user may disable the workaround when using another BMC firmware like
OpenBMC, u-bmc or some custom BMC bootloader with fast serial setup.

Change-Id: I7d6599b76384fc94a00a9cfc1794ebfe34863ff9
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36591
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-04 11:42:29 +00:00
Arthur Heymans a1b700ff74 arch/mips: Pass cbmem_top to ramstage via calling argument
This allows to use a common cbmem_top implementation.

Change-Id: I85efe3899607854c36d0ec594868f690eb724a7f
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36421
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-11-04 11:40:25 +00:00
Arthur Heymans 879c9fc421 soc/nvidia/tegra210: Populate _cbmem_top_ptr
On this platform the ramstage is run on a different core so passing
cbmem_top via calling arguments is not an option. To work around this
populate _cbmem_top_ptr with cbmem_top_chipset which is also used in
romstage.

Change-Id: I8799c12705e944162c05fb7225ae21d32a2a882b
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36557
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-04 11:40:12 +00:00
Arthur Heymans a09d33ec88 arch/ppc64: Pass cbmem_top to ramstage via calling argument
This avoids the need for a platform specific implementation of
cbmem_top.

HOW TO TEST? There is no serial console for the qemu target...

Change-Id: I68aa09a46786eba37c009c5f08642445805b08eb
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36276
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marty E. Plummer <hanetzer@startmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-11-04 11:39:25 +00:00
Kyösti Mälkki bc78e014c5 cpu/intel/car/p4-netburst: Remove delay loops
While commented as 10 ms + 250 us, those delay loops actually
accounted for a total of 840 ms. And they seem unnecessary
as followup code has potentially infinite retries when
polling for status changes.

Tested on aopen/dxplplusu, dual-socket P4 Xeon HT model_f2x.

Change-Id: Ib7d1d66ed29c62d97073872f0b7809d719ac2324
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36595
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-11-04 11:38:38 +00:00
Arthur Heymans a751eec799 cpu/intel/em64t101: Add Nehalem to compatibility list
Change-Id: I15a1c824b92e18f9963c60659ead92c988d1239b
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36588
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-11-04 11:37:54 +00:00
Arthur Heymans f6a8c5a493 cpu/intel/smm/gen1: Deal with SMM save state compatibility
Change-Id: I92326e3e0481d750cb9c90f717ed748000e33ad3
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36587
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-11-04 11:37:42 +00:00
Arthur Heymans 228f004f76 mb/*/*{i82801ix}: Use sb/intel/common/acpi/platform.asl
Change-Id: I9150db163131d4c3f99a4e0b6922a61c96a6d6e2
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36578
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-11-04 11:36:50 +00:00
Arthur Heymans 6c13b0427a mb/*/*{bd82x6x/ibexpreak}: Use sb/intel/common/acpi/platform.asl
Change-Id: I36095422559e6c160aa57f8907944faa4c192dee
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36577
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-11-04 11:36:39 +00:00
Arthur Heymans 8195aa02f9 sb/intel/common/platform.asl: Remove setting unused GNVS
Change-Id: I842af0a0e6435d33759649065b2b5a6f6d35071d
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36586
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-11-04 11:36:25 +00:00
Arthur Heymans a0365c5809 sb/intel/i82801jx/nvs.h: include required header
u8, u16, ... are defined in stdint.h.

Change-Id: I045438a7e754d4da936cf2ded411d055f2f69b45
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36556
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-04 11:35:35 +00:00
Arthur Heymans 6190d0bfe6 nb/intel/x4x/x4x.h: Include iomap.h
This is needed for the definition of the MCHBARx() macros.

Change-Id: I654344451c0568f306f39365fd07371b2d6cff04
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36555
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-04 11:35:25 +00:00
Elyes HAOUAS 085ab5a347 sb/intel: Move 'smbus.asl' to common place
Change-Id: Ia5b148c54224269bda98afe7c8a2c22c10a3bf56
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36500
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Guckian
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-11-04 11:35:16 +00:00
Arthur Heymans ca64305152 nb/intel/gm45: Build test with VBOOT
Change-Id: I21d20d7c575833ace02b4b8ed9d5c82750b331c7
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36238
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-11-04 11:34:59 +00:00
Arthur Heymans 41f826a498 mb/lenovo/{x200,t400}: Add VBOOT support
Tested on thinkpad X200 with CONFIG_H8_FN_KEY_AS_VBOOT_RECOVERY_SW
selected, the RW_A slot is properly selected unless the FN button is
pressed. 600+ms are spend waiting for the EC to be ready.

Change-Id: I689fe310e5b828f2e68fcbe9afd582f35738ed1d
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35998
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-04 11:34:53 +00:00
Kyösti Mälkki 334211e4a6 Documentation: Add some significant 4.11 release notes
Change-Id: I44369bc7dee77beab480d9a16cd7268be6686eb9
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36563
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Michael Niewöhner
2019-11-04 11:34:29 +00:00
Eric Lai 5407571168 mb/google/drallion: Update GPIO table
Follow latest GPIO table to change gpio.

BUG=b:143728355
BRANCH=N/A
TEST=build pass

Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: Iee61c74a5cab5a62a90c0543f212650c4f2420de
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36524
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mathew King <mathewk@chromium.org>
2019-11-04 11:33:44 +00:00
Eric Lai 3d4f51ef69 mb/google/drallion: Correct GPP_E7 as stop pin
Current design reset pin is connected to PLTRST.
GPP_E7 is stop pin for touch. Reserve reset pin for
next stage implement.

BUG=b:143733039
BRANCH=N/A
TEST=check touch screen can work properly

Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I3ebd56ab49b87da425583da04f082e69293a023e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36535
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mathew King <mathewk@chromium.org>
2019-11-04 11:33:32 +00:00
Eric Lai 1845fc8947 mb/google/drallion: fix GPP_E16 glitch when enter S5
Set GPP_E16 reset to DEEP.

BUG=b:143057255
BRANCH=N/A
TEST=Measure GPP_E16 from S0 to S5 has no glitch

Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I63932c6f5c8b7e6e9ab8aa55e69c629d29e7d1fe
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36511
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-by: Mathew King <mathewk@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-04 11:33:23 +00:00
Michael Niewöhner e979442cd6 payloads/external/GRUB2: fix constantly rebuilding due to git checkout
Multiple git checkouts cause GRUB2 to constantly rebuild even if there
were no changes to code or config. This is due to changing timestamps.

Fix this by not creating or switching branches but instead rely on
`git checkout -f` which does not touch existing unchanged files.

To be sure to not break anyones workflow checkout is skipped and a
warning gets printed if the tree/index is unclean.

Change-Id: I7cf66f63268de973a654146a0a47c3d5ca516d4d
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36343
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-04 11:33:17 +00:00
Wim Vervoorn 653a66fa81 vendorcode/eltan/security: Correct debug output
Correct debug ouput in tpm2_get_capability_pcrs.

BUG=N/A
TEST=build

Change-Id: Ibd12c9dc22980f21ecba204729c5da0d11618e12
Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36484
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-04 11:32:46 +00:00
Wim Vervoorn d1fb78dbfc vendorcode/eltan/security: Address layout issues
Corrected several layout issues in the mboot.c file.

BUG=N/A
TEST=build

Change-Id: I1599c7be075130345f018a08bede3eb849129a1c
Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36485
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
2019-11-04 11:32:16 +00:00
Mathew King be820b3911 smbios: Create a type for smbios_enclosure_type
Add a name to the SMBIOS enclosure type enum and use it as the return
type for smbios_mainboard_enclosure_type.

BUG=b:143701965
TEST=compiles

Change-Id: I816e17f0de2b0c119ddab638e57b0652f53f5b61
Signed-off-by: Mathew King <mathewk@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36516
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-04 11:31:12 +00:00