Commit Graph

37889 Commits

Author SHA1 Message Date
Angel Pons 7b4d67cf42 sec/intel/txt: Extract BIOS ACM loading into a function
Tested on Asrock B85M Pro4, still boots with TXT enabled.

Change-Id: I0b04955b341848ea8627a9c3ffd6a68cd49c3858
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46593
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-10-22 20:05:38 +00:00
Angel Pons 84641c8183 nb/intel/haswell: Add HASWELL_HIDE_PEG_FROM_MRC option
The MRC will perform PCI enumeration, and if it detects a VGA device in
a PEG slot, it will disable the IGD and not reserve any memory for it.
Since the memory map is locked by the time MRC finishes, the IGD can not
be enabled afterwards. Changing this behavior requires patching the MRC.

Hiding the PEG devices from MRC allows the IGD to be used even when a
dedicated graphics card is present. However, MRC will not program the
PEG AFE settings as it should, which can cause stability problems at
higher PCIe link speeds. Thus, restrict this workaround to only run when
the HASWELL_HIDE_PEG_FROM_MRC option is enabled. This allows the IGD to
be disabled and the PEG AFE settings to be programmed when a dedicated
graphics card is to be enabled, which results in increased stability.

The most ideal way to fix this problem for good is to implement native
platform init. Native init is necessary to make Nvidia Optimus usable.

Tested on Asrock B85M Pro4, using the PEG slot with a dedicated graphics
card as well as without. Graphics in both situations function properly.

Change-Id: I4d825b1c41d8705bfafe28d8ecb0a511788901f0
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45534
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-22 20:05:25 +00:00
Angel Pons 6c4028dd3d sec/intel/txt: Only run LockConfig for LT-SX
LockConfig only exists on Intel TXT for Servers. Check whether this is
supported using GETSEC[PARAMETERS]. This eliminates a spurious error for
Client TXT platforms such as Haswell, and is a no-op on TXT for Servers.

Change-Id: Ibb7b0eeba1489dc522d06ab27eafcaa0248b7083
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46498
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-10-22 20:05:01 +00:00
Angel Pons e70a3f8822 sec/intel/txt: Always run SCHECK on regular boots
When Boot Guard is disabled or not available, the IBB might not even
exist. This is the case on traditional (non-ULT) Haswell, for example.

Leave the S3 resume check as-is for now. Skylake and newer may need to
run SCHECK on resume as well, but I lack the hardware to test this on.

Change-Id: I70231f60d4d4c5bc8ee0fcbb0651896256fdd391
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46497
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-10-22 20:04:30 +00:00
Angel Pons 8a285fd8a5 sec/intel/txt: Allow skipping ACM NOP function
This is merely used to test whether the BIOS ACM calling code is working
properly. There's no need to do this on production platforms. Testing on
Haswell showed that running this NOP function breaks S3 resume with TXT.
Add a Kconfig bool to control whether the NOP function is to be invoked.

Change-Id: Ibf461c18a96f1add7867e1320726fadec65b7184
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46496
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-10-22 20:03:18 +00:00
Angel Pons c037695c19 sec/intel/txt/ramstage.c: Do not init the heap on S3 resume
It causes problems on Haswell: SINIT detects that the heap tables differ
in size, and then issues a Class Code 9, Major Error Code 1 TXT reset.

Change-Id: I26f3d291abc7b2263e0b115e94426ac6ec8e5c48
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46495
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-10-22 20:02:58 +00:00
Angel Pons 8f7e2a3add sec/intel/txt/ramstage.c: Extract heap init into a function
Heap initialization is self-contained, so place it into a separate
function. Also, do it after the MSEG registers have been written, so
that all register writes are grouped together. This has no impact.

Change-Id: Id108f4cfcd2896d881d9ba267888f7ed5dd984fa
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46494
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-10-22 20:01:54 +00:00
Angel Pons 08de7d6bbd sec/intel/txt: Add and fill in BIOS Specification info
This is not critical to function, but is nice to have.

Change-Id: Ieb5f41f3e4c5644a31606434916c35542d35617a
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46493
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-22 20:01:35 +00:00
Angel Pons 28d0408409 sec/intel/txt/common.c: Only log ACM error on failure
The TXT_BIOSACM_ERRORCODE register is only valid if TXT_SPAD bit 62 is
set, or if CBnT is supported and bit 61 is set. Moreover, this is only
applicable to LT-SX (i.e. platforms supporting Intel TXT for Servers).

This allows TXT to work on client platforms, where these registers are
regular scratchpads and are not necessarily written to by the BIOS ACM.

Change-Id: If047ad79f12de5e0f34227198ee742b9e2b5eb54
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46492
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-22 20:00:19 +00:00
Angel Pons 5a6daa6b72 sec/intel/txt: Move DPR size to Kconfig
Instead of hardcoding the size in code, expose it as a Kconfig symbol.
This allows platform code to program the size in the MCH DPR register.

Change-Id: I9b9bcfc7ceefea6882f8133a6c3755da2e64a80c
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46491
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-10-22 19:59:53 +00:00
Angel Pons 92eab64a43 configs: Add TXT-enabled config for Asrock B85M Pro4
This config selects the necessary options to enable Intel TXT on the
Asrock B85M Pro4, and allows the code to be build-tested. Note that the
current TXT code will not work, as it was written for Broadwell-DE.
Subsequent commits will adapt the code as necessary to work on Haswell.

Compatible BIOS and SINIT ACMs can be retrieved from a firmware update
for the Supermicro X10SLH. As they are not in the blobs repository, use
the STM binary as a placeholder so as to allow build-testing the code.

Change-Id: Ibf8db5fdfac5b527520023277c6370f6efa71717
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46489
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-22 19:59:30 +00:00
Marc Jones 985d956833 soc/intel/xeon_sp/skx/: Clean up soc_util.c
Remove unused c_util.c helper functions and clean up soc_util.h in
preparation for merging common code with cpx/.

Change-Id: Iff825f64b665aadcf8eac8a404191c0b74f92abd
Signed-off-by: Marc Jones <marcjones@sysproconsulting.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46094
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-22 17:03:49 +00:00
Marc Jones 97321db21d soc/intel/xeon_sp: Move common northbridge ACPI to nb_acpi.c
De-duplicate and prepare for common ACPI. Move common
northbridge ACPI code to nb_acpi.c. There are a few
differences between the skx and cpx defined FSP hob names
and CSTACKS that are managed with #if (CONFIG(SOC_INTEL_*_SP)).

Change-Id: I47ab1df3474d18643ef5ffc8199e09ea3dd32ccf
Signed-off-by: Marc Jones <marcjones@sysproconsulting.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45850
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-10-22 16:28:16 +00:00
Marc Jones 2560ad3233 soc/intel/xeon_sp/cpx: Add soc_acpi_fill_fadt()
Prepare for common ACPI code. Make acpi_fill_fadt() match
intel/commom/block/acpi/acpi.c function. Use soc_acpi_fill_fadt()
to set cpx fadt->flags.

Change-Id: I9c04dd478aa5e0f1467e63d06da094128edd9650
Signed-off-by: Marc Jones <marcjones@sysproconsulting.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45845
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-22 16:18:11 +00:00
Patrick Rudolph bc744f5893 drivers/smmstore: Implement SMMSTORE version 2
SMMSTORE version 2 is a complete redesign of the current driver. It is
not backwards-compatible with version 1, and only one version can be
used at a time.

Key features:
* Uses a fixed communication buffer instead of writing to arbitrary
  memory addresses provided by untrusted ring0 code.
* Gives the caller full control over the used data format.
* Splits the store into smaller chunks to allow fault tolerant updates.
* Doesn't provide feedback about the actual read/written bytes, just
  returns error or success in registers.
* Returns an error if the requested operation would overflow the
  communication buffer.

Separate the SMMSTORE into 64 KiB blocks that can individually be
read/written/erased. To be used by payloads that implement a
FaultTolerant Variable store like TianoCore.

The implementation has been tested against EDK2 master.

An example EDK2 implementation can be found here:
eb1127744a

Change-Id: I25e49d184135710f3e6dd1ad3bed95de950fe057
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Signed-off-by: Christian Walter <christian.walter@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40520
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2020-10-22 12:29:47 +00:00
Tim Chen a693fa06cd dedede: Create metaknight variant
Create the metaknight variant of the waddledee reference board by
copying the template files to a new directory named for the variant.

(Auto-Generated by create_coreboot_variant.sh version 4.2.0).

BUG=b:169813211
BRANCH=None
TEST=util/abuild/abuild -p none -t google/dedede -x -a
make sure the build includes GOOGLE_METAKNIGHT

Signed-off-by: Tim Chen <tim-chen@quanta.corp-partner.google.com>
Change-Id: Ia2e473eb1d0a2c819b874e497de0823fca75645a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46568
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-10-22 12:28:25 +00:00
Shelley Chen 17df7d634d security/vboot: Remove all tpm 1.2 functions for mrc hash in the tpm
Since MRC_SAVE_HASH_IN_TPM depends on TPM2, we can now remove the tpm
1.2 versions of functions that deal with mrc hash in the tpm as it
will not be used by tpm 1.2 boards.  Also move all antirollback
functions that deal with mrc hash in the tpm under CONFIG(TPM2).

BUG=b:150502246
BRANCH=None
TEST=make sure boards are still compiling on coreboot Jenkins

Change-Id: I446dde36ce2233fc40687892da1fb515ce35b82b
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46615
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-10-22 06:53:26 +00:00
Hung-Te Lin c47ed6e8c3 mb/google/asurada: Add Chrome OS GPIOs
Add the Chrome OS specific GPIOs (WP, EC, H1, ...) GPIOs.

BUG=None
TEST=emerge-asurada coreboot; # also boots into emmc
BRANCH=None

Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Change-Id: Ieeeee88a09ae4c3af15e2ae93a29684d30dde493
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46386
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-22 02:13:43 +00:00
Nicolas Boichat 5ed4d63fe1 mb/google/asurada: enable SPI devices
Configure and initialize EC and TPM on Asurada.

BUG=none
TEST=boot asurada

Change-Id: I0f169407d1726899fd0c42e144d907024f036c6a
Signed-off-by: Yidi Lin <yidi.lin@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46385
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-22 02:13:15 +00:00
Ikjoon Jang aa752158a6 soc/mediatek/mt8192: enable CONFIG_ARM64_USE_ARM_TRUSTED_FIRMWARE
BRANCH=none
BUG=b:159079785
TEST=1. Checkout https://review.trustedfirmware.org/c/4334
     2. emerge-asurada coreboot chromeos-bootimage
     3. boot asurada

Change-Id: Ieb93073beff7ec95eb5406eecbfba8192f91edce
Signed-off-by: Ikjoon Jang <ikjn@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46382
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-22 02:12:36 +00:00
Yidi Lin cbbdcb330d soc/mediatek/mt8192: Add board-specific regulator APIs
To enable DVFS, DRAM driver needs to access four different
regulators that SoC can't access directly and need board-specific
implementations.

To support that we need to define the getter and setter APIs for
those regulators.

BUG=b:147789962
BRANCH=none
TEST=verified with DRAM driver

Signed-off-by: Yidi Lin <yidi.lin@mediatek.com>
Change-Id: I0c2d471a7f8628735af90c5b5a5ab3012831e442
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46405
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-22 02:12:14 +00:00
Duncan Laurie 3502960e50 acpigen: Make acpigen_write_opregion() argument const
This structure is not modified so it can be made const and allow
the calling function to also declare it as a const structure.

Signed-off-by: Duncan Laurie <dlaurie@google.com>
Change-Id: Id8cdfb4b3450a5ab2164ab048497324175b32269
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46258
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-21 22:24:27 +00:00
Duncan Laurie 30c3f91d33 acpigen: Make gpio set/get arguments const
The 'struct acpi_gpio' arguments passed to acpigen functions are
not modified so they can be made const, which allows drivers to
also use a const pointer.

Signed-off-by: Duncan Laurie <dlaurie@google.com>
Change-Id: I59e9c19e7bfdca275230776497767ddc7f6c52db
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46257
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-21 22:24:19 +00:00
Duncan Laurie 36858208e6 acpigen: Add ShiftLeft function helper
Provide a helper function for the ACPI shift left operator that
uses the same operator for the source and result.

ShiftLeft (OP, count, OP)

Signed-off-by: Duncan Laurie <dlaurie@google.com>
Change-Id: I66ee89bd1c4be583d0e892b02535bfa9514d488a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46256
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-21 22:24:11 +00:00
Duncan Laurie 8e391d3452 acpigen: Add helpers for common Store operations
Add helpers for some store operations:

Store(INTEGER, NAME) ex: Store (100, SAVE)
Store(INTEGER, OP)   ex: Store (100, Local0)

Change-Id: Ia1b3f451acbfb2fc50180a8dcd96db24d330c946
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46255
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-21 22:24:03 +00:00
Duncan Laurie 095bbf969d acpigen: Add option for reserved bits in Field
Add an option for unused/reserved bits in a Field definition,
allowing for declarations that do not start at bit 0:

Field (UART, AnyAcc, NoLock, Preserve)
{
    , 7,  /* RESERVED */
    BITF, /* Used bit */
}

These just use byte 0 instead of a name.

Change-Id: I86b54685dbdebacb0834173857c9341ea9fa9a46
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46254
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-21 22:23:55 +00:00
Srinidhi N Kaushik cf5d58328f drivers/intel/gma: Increase vbt_data size
With TGL FSP v3373 onwards vbt binary size changed from 8KiB
to 9KiB. Due to which cbfsf_decompression_info check failed
when trying to load vbt binary from cbfs because vbt
decompressed_size was greater than vbt_data size. This caused
Graphics init and fw screen issues. Increase the vbt_data to
9KiB to accommodate new vbt binary.

BUG=b:170656067
BRANCH=none
TEST=build and boot delbin and verify fw screen is loaded

Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Change-Id: If6ffce028f9e8bc14596bbc0a3f1476843a9334e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46374
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Dossym Nurmukhanov <dossym@google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2020-10-21 18:36:08 +00:00
Patrick Rudolph 3e69c0a077 cpu/intel/common: Fix regression
Fix the logic introduced in CB:46276
"cpu/intel/common: only lock AES-NI when supported"
which needs to be negated.

Change-Id: Icaf882625529842ea0aedf39147fc9a9e6081e43
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46634
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-21 17:52:24 +00:00
Duncan Laurie 389cb30ced soc/intel/common: Fix/clean up USB4 PCIe virtual/generic driver
This driver is for the root port device and needs to reference the
parent device for its ACPI scope.  Similarly for the debug output it
needs to use the parent device, and fall back to the chip name if
config->desc is not provided in the devicetree.

The UID property is removed.  This value is not the same as the port
number; according to some docs it should be unique but it is not fully
clear what it should be tied to.  Regardless, it is not used by the
Thunderbolt driver in the kernel.

I also renamed some functions/structures to be clear that this is just
an ACPI driver for the PCIe root port and not a driver for the root port
itself.  As part of this I removed the PCI based resource operations and
the scan bus function since this device does not have children itself.

Finally I added a detailed comment with an example describing what the
driver is for and what properties it generates.

TEST=boot on volteer and ensure the USB4 root port device and properties
are added to the SSDT as described by the comment in chip.h.

Signed-off-by: Duncan Laurie <dlaurie@google.com>
Change-Id: Id6069a0fb7a0fc6836ddff1dbeca5915e444ee18
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46544
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-21 15:35:50 +00:00
Duncan Laurie fcbf18c5df soc/intel/common: Fix ACPI device name for USB4 DMA device
The USB4 host interface (DMA) devices need to use SA_DEVFN_*
instead of SA_DEV_* when determining the ACPI name.

The matching names are removed from the SOC-level ACPI name
handler since they are provided by this driver now.

TEST=boot on volteer and ensure TDM0 device is in the SSDT.

Signed-off-by: Duncan Laurie <dlaurie@google.com>
Change-Id: If778bda82b80593452a590962dbffef6eff6484a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46543
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-10-21 15:35:42 +00:00
Duncan Laurie bf69622256 device: Allow virtual/generic devices under PCI in devicetree
This change allows a generic device to be described in the devicetree
under a PCI device, such as a root port.

Previously any device under a PCI device was expected to also be a PCI
device and that does not allow for a virtual/generic device to be
present, for example to provide ACPI properties for a root port.

The changes are:
- Ignore non-PCI devices found under a PCI device when scanning and do
not print an error for each devfn scanned.
- Don't treat non-PCI devices as leftover and remove them, instead
enable them as a static device.
- Don't attempt to configure a static device in the tree that is not a
PCIe device type.

With these changes it is now possible to have a generic device under a
PCI device, for example in a USB4/TBT root port (PCIe hotplug device)
this generic device will add ACPI properties for the PCIe tunnel routed
to the external port:

device pci 07.0 on
  chip soc/intel/common/block/pcie
    device generic 0 on end
  end
end

TEST=boot on volteer with the USB4 root port devices in chipset.cb and
ensure they are enabled properly and there are no errors printed in the
coreboot log, and that the device properties are created in the SSDT.

Signed-off-by: Duncan Laurie <dlaurie@google.com>
Change-Id: I56a491808067dc862a7adfd46852f0bd6b41cd95
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46542
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-21 15:35:33 +00:00
Duncan Laurie 3e4a14e153 device: Export enable_static_device() function
The work done by enable_static_devices() and scan_generic_bus()
is common and can be used by other device handlers to enable a
single static device.

Signed-off-by: Duncan Laurie <dlaurie@google.com>
Change-Id: Ibfde9c4eb794714ebd9800e52b91169ceba15266
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46541
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-10-21 15:35:24 +00:00
Nico Huber 2a507f734e mb/asus/f2a85-m_pro: Turn super-i/o 0x30 writes into on/off
The 0x30 register is eventually controlled by coreboot's
pnp_enable_resources() based on the on/off setting. Other
register settings were grouped with their respective "virtual"
LDN, where possible.

Note, this temporarily breaks LDN 8 settings, as coreboot will
ignore configuration for disabled devices.

Change-Id: I8585dd08eed407ab12258f2accaa63dab294e7d8
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46014
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-10-21 14:49:15 +00:00
Nico Huber 9f7b36a540 mb/asus/f2a85-m_pro: Use `irq` in dt for single-byte registers
The `io` statement will prepare a 16-bit write, hence use `irq` for
miscellaneous 8-bit registers and fix actual `io` settings (i.e. merge
0x61 writes into 0x60). Note, using `irq` is still just a hack as these
are neither I/O nor IRQs, but it's common practice in coreboot.

Change-Id: I2e1c2286be726d126598cc4a97bb15a57faef42f
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46013
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-10-21 14:37:48 +00:00
Paul Menzel 947dc64d21 mb/asus/f2a85-m_pro: Enable keyboard controller in devicetree
The mainboard has a PS/2 port, so enable the keyboard controller in the
devicetree.

The PS/2 keyboard now works in SeaBIOS payload, but not in GNU/Linux,
probably as ACPI code still needs to be added.

Change-Id: I7846633bc1a3bdf6bffae628e0542bb8fb684804
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45998
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-10-21 14:37:38 +00:00
Felix Held 4fc4a37038 3rdparty/amd_blobs: update submodule pointer
This now tracks a recently created upstream repository located at
https://github.com/amd/firmware_binaries

BUG=b:166107781

Change-Id: Ib193d646bb51cbf7b86f46828033e619c3f70e16
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46594
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-21 13:45:30 +00:00
Kevin Chiu 9cc148d8c5 mb/google/zork: update USB 2.0 controller Lane Parameter for morphius
Enhance USB 2.0 SI by increasing the level of "HS DC Voltage Level"
and "Disconnect Threshold Adjustment".
COMPDISTUNE0: 0x3->0x7
TXVREFTUNE0: 0x6->0xf

BUG=b:162614573
BRANCH=zork
TEST=1. emerge-zork coreboot
     2. check U2 registers are set correctly
     3. test with servo v4 type-c, it's working expectedly.
     4. U2 SI pass

Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com>
Change-Id: I278cc0aaddbc9fce595bf57ca69ee8abfc9f5659
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46537
Reviewed-by: Rob Barnes <robbarnes@google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-21 12:53:17 +00:00
Kevin Chiu 0088b3df28 mb/google/zork: Update telemetry settings for morphius
Correct the two load line slope settings for the SVID3 telemetry.
AGESA sends these values to the SMU, which accepts them as units
of current.  Proper calibration is determined by the AMD SDLE tool
and the Stardust test.

BUG=b:168265881
BRANCH=zork
TEST=emerge-zork coreboot

Change-Id: Id6c4f1a92d7f2ad293df7b63694e9665b85f8018
Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46472
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Chris Wang <chris.wang@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-21 12:48:12 +00:00
Michael Niewöhner fb620109a4 mb/google/dedede: drop obsolete ISST workaround
Early JSL silicon hang while booting Linux with ISST enabled. The
malfunctioning silicon revisions have been used only for development
purposes and have been phased out. Thus, drop the ISST workaround.

Change-Id: Ic335c0bf03a5b07130f79c24107a1b1b0ae75611
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46459
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-10-21 12:38:08 +00:00
Michael Niewöhner 63032439f4 {cpu,soc}/intel: replace AES-NI locking by common implemenation call
Deduplicate code by using the new common cpu code implementation of
AES-NI locking.

Change-Id: I7ab2d3839ecb758335ef8cc6a0c0c7103db0fa50
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46278
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-10-21 12:34:28 +00:00
Paul Menzel 2ac743330c mb/asus/f2a85-m_pro: Enable UART A in Super I/O
Currently, the serial console does not work.

With the serial port enabled in the vendor firmware, `superiotool` outputs
the global control register values below.

    Found Nuvoton NCT6779D (id=0xc562) at 0x2e
    Register dump:
    idx 10 11 13 14 1a 1b 1c 1d  20 21 22 24 25 26 27 28  2a 2b 2c 2f
    val ff ff ff ff 3a 28 00 10  c5 62 df 04 00 00 10 00  48 20 00 01
    def ff ff 00 00 30 70 10 00  c5 62 ff 04 00 MM 00 00  c0 00 01 MM

UART A needs to be enabled in CR 0x2a by clearing bit 7. Do this by
selecting the Super I/O Kconfig symbol `SUPERIO_NUVOTON_COMMON_COM_A`.
This changes the default value 0xc0 to 0x40.

Note, due configuring the system as legacy free with
`HUDSON_LEGACY_FREE=y`, AGESA in romstage disables the LPC controller in
`FchInitResetLpcProgram()`.

    coreboot-4.12-3417-g192b9576fe Tue Oct 20 09:15:53 UTC 2020 romstage starting (log level: 7)...
    APIC 00: CPU Family_Model = 00610f31

    APIC 00: ** Enter AmdInitReset [00020007]
    Fch OEM config in INIT RESET

`AmdInitReset() returned AGESA_SUCCESS` is not transmitted anymore. Only
when coreboot enables the LPC controller again in ramstage, serial output
continues.

    PCI: 00:14.4 bridge ctrl <- 0013
    PCI: 00:14.4 cmd <- 00
    PCI: 00:14.5 cmd <- 02
    PCI: 00:15.0 bridge ctrl <- 0013
    PCI: 00:15.0 cmd <- 00
    PCI: 00:15.1 bridge ctrl <- 0013
    […]
    done.
    BS: BS_DEV_ENABLE run times (exec / console): 0 / 30 ms
    Initializing devices...
    CPU_CLUSTER: 0 init
    […]

Note, due to incorrect Super I/O configuration in the devicetree, the boot
hangs in `PCI: 00:14.3 init` when doing `outb(0, DMA1_RESET_REG)`. This
will be fixed in follow-up commits.

TEST=Receive (some) coreboot log messages over the serial console.
Change-Id: I0aa367316f274ed0dd5964ba5ed045b9aeaccf8d
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39371
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-10-21 12:29:44 +00:00
Patrick Georgi 8fed9d638d mb/supermicro/x11-lga1151-series: Follow up GPIO macro changes
Following commit f50ea988b a couple of symbols are gone, so follow up
that change for this board as well.

Change-Id: I09fd3a107447eb45bb46b7f0f821377943f140b2
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46621
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-21 10:09:40 +00:00
Michael Niewöhner f50ea988b0 soc/intel,mb/*: get rid of legacy pad macros
Get rid of legacy pad macros by replacing them with their newer
equivalents.

TEST: TIMELESS-built board images match

Change-Id: I078f9bb3c78f642afc6dcfd64d77be823a4485c2
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46567
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-10-21 07:16:01 +00:00
Michael Niewöhner dadcbfbe8c soc/intel: convert XTAL frequency constant to Kconfig
This converts the constant for the XTAL frequency to a Kconfig option.

Change-Id: I1382dd274eeb9cb748f94c34f5d9a83880624c18
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46018
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-10-21 07:14:00 +00:00
Michael Niewöhner fe6070f728 soc/intel/common: add Kconfig for PM Timer emulation support
Add a Kconfig for SoCs to indicate PM ACPI timer emulation support and
select it by the appropriate SoCs.

This Kconfig gets used in the follow-up changes.

Change-Id: I6ded79221a01655f298ff92b8bd2afabd1d2a3ff
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46017
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-10-21 07:13:22 +00:00
Sumeet R Pawnikar 7ea4372d82 mb/google/dedede/variants/drawcia: update PL1 max and min power values
Update PL1 max and min power values

BUG=None
BRANCH=None
TEST=build and verify on dralat system

Change-Id: I75d47fa721576564f71fbd5d5fd2e820fc3f1925
Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46502
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2020-10-21 07:13:03 +00:00
Shelley Chen a45f8959c0 mrc_cache: Remove unnecessary data checksum calculation
When MRC_SAVE_HASH_IN_TPM is selected, we can just use the TPM hash to
verify the MRC_CACHE data.  Thus, we don't need to calculate the
checksum anymore in this case.

BUG=b:150502246
BRANCH=None
TEST=make sure memory training still works on nami

Change-Id: I1db4469da49755805b541f50c7ef2f9cdb749425
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46515
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-10-20 23:26:15 +00:00
Shelley Chen c1040f3ef4 mrc_cache: Add tpm_hash_index field to cache_region struct
Pull selection of tpm hash index logic into cache_region struct.  This
CL also enables the storing of the MRC hash into the TPM NVRAM space
for both recovery and non-recovery cases.  This will affect all
platforms with TPM2 enabled and use the MRC_CACHE driver.

BUG=b:150502246
BRANCH=None
TEST=make sure memory training still works on nami and lazor

Change-Id: I1a744d6f40f062ca3aab6157b3747e6c1f6977f9
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46514
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-10-20 23:26:01 +00:00
Shelley Chen df0481e9e1 security/vboot: Add new TPM NVRAM index MRC_RW_HASH_NV_INDEX
Add new index for MRC_CACHE data in RW.  Also update antirollback
functions to handle this new index where necessary.

BUG=b:150502246
BRANCH=None
TEST=make sure memory training still works on nami

Change-Id: I2de3c23aa56d3b576ca54dbd85c75e5b80199560
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46511
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-10-20 23:25:50 +00:00
Shelley Chen a79803cf29 security/vboot: Make mrc_cache hash functions generic
We need to extend the functionality of the mrc_cache hash functions to
work for both recovery and normal mrc_cache data.  Updating the API of
these functions to pass in an index to identify the hash indices for
recovery and normal mode.

BUG=b:150502246
BRANCH=None
TEST=make sure memory training still works on nami

Change-Id: I9c0bb25eafc731ca9c7a95113ab940f55997fc0f
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46432
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-10-20 23:25:39 +00:00