Commit Graph

36891 Commits

Author SHA1 Message Date
Patrick Rudolph 7f29896c77 soc/intel/cannonlake: Add PCIe ports on PCH-H
Fixes complains about missing INT configuration by the pciexp kernel
modules.

Tested with Linux 5.5 on Prodrive Hermes.

Change-Id: I277f592cd8d2c86a9c7ba4b34d3f703f7d593582
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45065
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-09-09 10:36:11 +00:00
Angel Pons c6c9b9cf48 apollolake: Define MAX_CPUS at SoC scope
The three Intel Apollo Lake boards (apl_rvp, leafhill and minnow3) do
not define MAX_CPUS, which would then default to 1. Since this is most
likely an oversight, use the same value as other Apollo Lake boards.

To ensure this does not happen again, factor out MAX_CPUS to SoC scope.

Change-Id: I5ed98a6b592c8010b59eca7ff773ae1ccc4cd7b1
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45144
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-09 10:35:34 +00:00
Angel Pons c95f507fc7 apollolake: Limit MAX_CPUS to 4
APL does not support Hyper-Threading, and has at most four CPU cores.

Change-Id: Ib2ffadc0c31cdd96bec8eed5364c984acb2e1250
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45143
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-09 10:35:13 +00:00
Angel Pons f4779e8679 geminilake: Factor out MAX_CPUS value
Both Gemini Lake boards in the tree use the same value.

Change-Id: Ib6bd05206026736fd7e3d44b49e4d8ba217c2708
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45142
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-09-09 10:34:51 +00:00
Angel Pons b36100faf4 soc/intel/apollolake: Rename `SOC_INTEL_GLK` symbol
For consistency with other platforms, use `SOC_INTEL_GEMINILAKE`.

Change-Id: I06310e5a9bca6c9504f19a6c2fe9b26626f290d4
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45141
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-09-09 10:34:32 +00:00
Subrata Banik ee73594575 vendorcode/intel/fsp/fsp2_0/adl: Add FSP header file version 1332
List of changes:
1. Select FSP_HEADER_PATH
2. Select FSP_FD_PATH
3. Select PLATFORM_USES_FSP2_2
4. Select UDK_202005_BINDING

Change-Id: Ic5b09bad3c23b84c6ff6b1ea9e1dc684d7463c27
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45148
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
2020-09-09 05:16:34 +00:00
David Wu 299cb4bb8a mb/google/puff: Increase DPTF parameters for faffy
Update critical and passive policy for TSR0.

BUG=b:167477885
BRANCH=puff
TEST=build and verify by thermal team

Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: I244e1b5cacabf5b73c47b4039ae150cd17fcd0fc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45169
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Reviewed-by: Sam McNally <sammc@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-09 00:11:58 +00:00
Julius Werner 8e0f9f30f6 3rdparty/qc_blobs: Uprev to new HEAD (6b7fe498eb)
Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: I2de0c13000e5b1e32e9c1a6de3daa09acf6c321b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45057
Reviewed-by: Philip Chen <philipchen@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-09 00:02:00 +00:00
Paul Fagerburg 40488bdcd1 src/mb/google/hatch: remove "sushi" variant.
Sushi is not a real product, just a test of the new_variant program.
The effort to keep it up-to-date with the rest of Hatch is no longer
worth it. Remove the variant.

BUG=b:168030592
TEST=build bot is successful, hatch-cq builds successfully

Signed-off-by: Paul Fagerburg <pfagerburg@chromium.org>
Change-Id: I2b0036f3cbdea4bfaed1274ab87a20d24c75de57
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45175
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-09-08 22:02:20 +00:00
Karthikeyan Ramasubramanian 68aed150b9 mb/google/dedede: Fix the SPD path
CB:44774 introduced the non-existent SPD path. This is preventing the
device from booting up.

BUG=b:168053219
TEST=Build and boot drawcia board to OS.

Change-Id: I70ca5f4cf2c8e2e88ea5b1514b656caafb732743
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45182
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-09-08 21:40:17 +00:00
Subrata Banik 9209817ace pci_ids: Add Alder Lake DTT PCI IDs
Add PCI IDs for Intel's Dynamic Tuning Technology (DTT) for ADL.

Also add NULL terminator at end of pci_device_ids.

Change-Id: If25b1f562567a833683b0b8796bd1d6cac0bd490
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45140
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-08 12:56:58 +00:00
Subrata Banik 627371722c pci_ids: Add Alder Lake IPU PCI IDs
Add PCI IDs for Intel's Image Processing Unit (IPU) for ADL.

Also add NULL terminator at end of pci_device_ids.

Change-Id: I327828d676422fc6162fadffd9b39529ecb89ace
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45139
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-09-08 12:56:51 +00:00
Michael Niewöhner 856731d3ba lib/Kconfig: Drop obsolete help text from GENERIC_SPD_BIN
SMBus code is linked unconditionally since commit 0e3c59e. This change
drops that obsolete part from the help text.

Change-Id: I603ab012760684021be1b5eca5d0ddff69463b79
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45145
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-09-08 05:47:33 +00:00
Michael Niewöhner f23794cf04 util/spd_tools: output binaries instead of hexdumps
Instead of generating hexdumps, output binary SPD files since we plan to
convert all hex SPD files to binary. Also adjust the file extension
where needed.

Test: compared generated binaries with converted binaries from hex files

Change-Id: Ie99d108ca90758d09dbefad20fe6c9f7fc263ef1
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44878
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-09-08 05:46:41 +00:00
Michael Niewöhner e10efa3a03 util/apcb_edit: fix handling of binary SPD files
Passing binary SPD files to apcb_edit can lead to an encoding error,
since the files were read in text mode. To fix this, read SPD files
always in binary mode and only decode them, when `--hex` is set.

Tested by comparing output files from the same SPDs in both, binary and
hex mode.

Change-Id: I6b75a9e1234e71667bdc8cb4eb10daf8c0ac3c17
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44778
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Rob Barnes <robbarnes@google.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-09-08 05:44:28 +00:00
Johnny Lin 9da0279e1a mb/ocp/deltalake: Add SMBIOS OEM string for SPD register vendor ID
Tested=On OCP Delta Lake, with FSP WW36 dmidecode -t 11 can see the
SPD register vendor ID
String 7: b300 0000 b300 0000 b300 0000 b300 0000 b300 0000 b300 0000

Change-Id: I15ab9b4c709eb97a03d6e08fe0bcdcb7f8607db0
Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44545
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-09-08 05:39:09 +00:00
Johnny Lin e4d27f6b4f vc/intel/fsp/fsp2_0/cpx_sp: Add DIMM definition in SystemMemoryMapHob
Most of them are needed for SMBIOS type 17 creation.

Tested=With FSP WW36 verified the printed hob values match
with FSP hob data.

Change-Id: I02f4600f1be39e2576d7c84a5a6b6672ebb7034b
Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44847
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-08 05:38:59 +00:00
CK Hu af0b00fa4d soc/mediatek/mt8192: Add SPI flash controller dual read function
Support SPI flash dual read funciton which change spi mode (1-1-1)
to dual mode (1-1-2).

Signed-off-by: CK Hu <ck.hu@mediatek.com>
Change-Id: Iabd3668fc4bc42137b7743144fc1cced4fe72737
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44852
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-08 05:38:36 +00:00
Subrata Banik 60296aec76 util/ifdtool: Add NULL check for pointer fpsba
This patch adds NULL check inside get_ifd_version_from_fcba()
function to fix Klocwork issue.

BUG=b:153888802

Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Change-Id: I525054376b36c658b93760b185ef6dd170f5aea9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45130
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2020-09-08 05:37:36 +00:00
Jonathan Zhang 5bb89e7f0c vendorcode/intel/FSP2_0/CPX-SP: update to ww36
Intel CPX-SP FSP ww36 release has following changes:
* Update FSP header version to change among FSP releases.
* Add SPDRegVen field in memory map HOB, to facilitate SMBIOS type 11
(OEM strings) generation.

Signed-off-by: Jonathan Zhang <jonzhang@fb.com>
Change-Id: I7a8dab3987c2f8f471b40f7b3b9ced0c2909271d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45100
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-08 05:36:34 +00:00
Jeremy Soller 27dd66aca7 mb/system76/lemp9: update HDA pin config
To minimize the quirks the kernel has to apply, the headset mic is set
to its correct value in coreboot.

Tested on lemp9, audio is functional.

Signed-off-by: Jeremy Soller <jeremy@system76.com>
Change-Id: I6b59de95f01360a5f7779f87f39edeb75dedc215
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43631
Reviewed-by: Michael Niewöhner
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-08 05:35:56 +00:00
Angel Pons 3406a4afef soc/intel/baytrail: Add missing GSM size definitions
Change-Id: I456591f63f463c5cec1cbf3c1633bdb61be92d29
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44935
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-08 05:34:55 +00:00
Elyes HAOUAS 463939f7a6 soc/intel/denverton_ns/Kconfig: Drop unused 'IQAT_MEMORY_REGION_SIZE'
Change-Id: I25cfc61b7a25b68dd22573a88933e03931a755ef
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45069
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Guckian <d.guckian20@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-09-08 05:34:12 +00:00
Elyes HAOUAS f2a2ea2490 mb/asus/a88xm-e/Kconfig: Correct 'HUDSON_XHCI_ENABLE' symbol
Change-Id: Ibe8844db74b43009e7c49df78882ed76b0bbebae
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45068
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-09-08 05:33:55 +00:00
Elyes HAOUAS 93fe99fec5 mb/opencellular/elgon/Kconfig: Drop unused 'MAINBOARD_FIT_DTS'
Change-Id: Ie084f93998dc16450bb3db99d7240905bed3d50e
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45067
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-09-08 05:33:39 +00:00
Johnny Lin 2afb5cf8b1 vendorcode/intel/fsp/fsp2_0/cpx_sp: Set correct stack number for IOU3
PSTACK2 (IOU3) should be stack number 4, mainboard uses stack number as
the index to access the bus number array read by get_stack_busnos().
Without the fix it would get the wrong bus number (0xb1).

Tested=On OCP Delta Lake, dmidecode -t 9 to verify slots bus number on
IOU3 are correct (0xb2).

Change-Id: I1c9e49bbc9a00de82d1fc67b3b4ed47e03eacdda
Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45022
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-09-08 05:32:37 +00:00
Karthikeyan Ramasubramanian 4d761db7e8 mb/google/dedede/var/drawcia: Configure I2C high and low time
Configure the I2C bus high and low time for all enabled I2C buses.

BUG=b:162232776
TEST=Measured the I2C bus frequency as 389 KHz, high time as 870 ns and
low time as 1580 ns.

Change-Id: I67d2725a7fc8d83e3fa8a56cfa86540c4e6f0971
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45084
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-08 05:32:24 +00:00
Karthikeyan Ramasubramanian 9526c5deda mb/google/dedede/var/waddledee: Configure I2C high and low time
Configure the I2C bus high and low time for all enabled I2C buses.

BUG=b:163743035
TEST=Measured the I2C bus frequency as 384 KHz, high time as 924 ns and
low time as 1680 ns.

Change-Id: I60a5f6814fb9818c724f6b6fe465ea49d0de0f97
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45083
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-08 05:32:14 +00:00
Srinidhi N Kaushik dc87025ce4 soc/intel/tigerlake: Skip GPIO configuration from FSP
FSP v3333 or later, provides a new UPD to Skip configuring
GPIO settings from FSP. coreboot should provide all the
required GPIO configuration for the platform when this UPD
is set.

BUG=b:166790597, b:146390704
BRANCH=none
TEST=build and boot volteer proto2

Cq-Depend:chromium-internal:3240396,chromium-internal:2870145
Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Change-Id: If32f35a188d510db8e4d8973cae78297d49a9240
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44913
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-08 05:31:35 +00:00
Srinidhi N Kaushik 6727276a65 vendorcode/intel/fsp: Update Tiger Lake FSP Headers for FSP v3333
Update FSP headers for Tiger Lake platform generated based FSP
version 3333. Previous version was 3313.
Changes Include:
1. Update comments
2. Add new UPD for Gpio Override support

BUG=b:166790597
BRANCH=none
TEST=build and boot volteer proto2

Cq-Depend:chromium-internal:3240396,chromium-internal:2870145
Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Change-Id: Ie3f0688143eef532946c7a2141909c1ac173fc2f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44912
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-08 05:31:16 +00:00
Tan, Lean Sheng aab188174f soc/intel/elkhartlake: Update SA & PM related definitions
1. Update SA base address & size
2. Update GBE control bit register value

Signed-off-by: Tan, Lean Sheng <lean.sheng.tan@intel.com>
Change-Id: I1f5036c9cd75682fcf239170bcb257ffaa002e7d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45077
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2020-09-08 05:30:44 +00:00
Tan, Lean Sheng b369dde9b1 soc/intel/elkhartlake: Update PMC related register definitions
Update ABase, PMC GPIO value sets and PMC register base address.

Signed-off-by: Tan, Lean Sheng <lean.sheng.tan@intel.com>
Change-Id: Iba43b791cab0665ddebfbed68b7e2d15406ad206
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45075
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2020-09-08 05:30:20 +00:00
Tan, Lean Sheng 9440c53567 soc/intel/elkhartlake: Add CPU, SA, PCH & IGD DIDs Table
1. Add CPU, SA, PCH & IGD DIDs table into report_platform.c
2. Add additional EHL SA DID in pci_ids.h

Signed-off-by: Tan, Lean Sheng <lean.sheng.tan@intel.com>
Change-Id: I5c98089873b17f82560eba13c7de3353b6d3e249
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45074
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2020-09-08 05:30:08 +00:00
Tan, Lean Sheng 70a2ddc5ac soc/intel/elkhartlake/acpi: Copy acpi directory from jasperlake
Clone entirely from Jasperlake

List of changes on top off initial jasperlake clone
1. Rename from jasperlake to elkhartlake
2. Remove irelevant devices asls (ipu,ish,camera clock,gpio_op)

Signed-off-by: Tan, Lean Sheng <lean.sheng.tan@intel.com>
Change-Id: I5e77081d1673cc0ca97edc63e9996c045ab6e9b0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44812
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-08 05:29:52 +00:00
Tan, Lean Sheng 05dfe3177d soc/intel/elkhartlake: Do initial SoC commit till ramstage
Clone entirely from Jasperlake

List of changes on top off initial jasperlake clone
1. Replace "Jasperlake" with "Elkhartlake"
2. Replace "jsl" with "ehl"
3. Replace "jsp" with "mcc"
4. Rename structure based on Jasperlake with Elkhartlake
5. Clean up upd override in fsp_params.c will be added later
6. Sort #include files alphabetically as per comment
7. Remove doc details from espi.c until it is ready
8. Remove pch_isclk & camera clocks related codes
9. Add new #define NMI_STS_CNT & NMI_EN as per comment

Signed-off-by: Tan, Lean Sheng <lean.sheng.tan@intel.com>
Change-Id: I372b0bb5912e013445ed8df7c58d0a9ee9a7cf35
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44802
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2020-09-08 05:29:37 +00:00
Angel Pons 320f2c1f06 soc/intel/apollolake: Hook up ENABLE_VMX
Unlike other platforms, Apollo and Gemini Lake have VmxEnable on FSP-S.

Note that this will enable VMX by default on both of these platforms.

Change-Id: I6a4470e0e64b10f07edfcf270bb02c7cd6a8fa1a
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45039
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by:  Felix Singer <felixsinger@posteo.net>
2020-09-08 05:28:05 +00:00
Angel Pons ae0d8d69db soc/intel/apollolake: Select CPU_INTEL_COMMON
This is an intermediate step to have SOC_INTEL_COMMON_BLOCK_CPU select
CPU_INTEL_COMMON directly, to avoid dependency problems.

Tested with BUILD_TIMELESS=1, UP Squared does not change.
Gemini Lake already selects this through SOC_INTEL_COMMON_BLOCK_SGX.

Change-Id: If737fa6d8700f435c8692c80244f0e71657c2236
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45038
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by:  Felix Singer <felixsinger@posteo.net>
2020-09-08 05:27:52 +00:00
Angel Pons 1057519074 nb/intel/ironlake: Use an enum for `gpu_panel_port_select`
The PRM does not describe the relevant bits, but Linux's i915 driver
handles these bits the same way for both Ironlake and Sandy Bridge.

Change-Id: Ice7412e335752bd7e297ad50f685effcefbd41d2
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45036
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-09-08 05:27:26 +00:00
Angel Pons dc0c081001 nb/intel/sandybridge: Use an enum for `gpu_panel_port_select`
All boards currently have backlight on either LVDS or eDP.

Change-Id: I878bc7f1ff75a2b82b9556e855aff1d4d03e0268
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45035
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-09-08 05:27:08 +00:00
Angel Pons d04957970c nb/intel/haswell: Drop `gpu_panel_port_select`
The corresponding bits in PP_ON_DELAYS are reserved MBZ.

Change-Id: Icd2554c928a5908dfb354b81d3e6c5b5f242f1d1
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45034
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-09-08 05:26:49 +00:00
Angel Pons f8d47455f7 soc/intel/broadwell: Drop `gpu_panel_port_select`
The corresponding bits in PP_ON_DELAYS are reserved MBZ.

Change-Id: I9789a7d50c4bce2ccad0bf476f877db25e3ff82e
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45033
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-09-08 05:26:25 +00:00
Mark Hsieh 657edbeea4 mb/google/volteer: config QS silicon devices for CSE LITE
Configure eldrid to use CSE Lite.

BUG=b:158140797
TEST=cd to volteer's asset_generation folder, execute
"./gen_all_variant_images.sh" and verify that all variant
images are produced.

Signed-off-by: Mark Hsieh <mark_hsieh@wistron.corp-partner.google.com>
Change-Id: I357abdac4102f358d3aa1cb50f600312039ef140
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45018
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
2020-09-08 05:26:02 +00:00
Tim Wawrzynczak 0cded1f116 soc/intel/tigerlake: Add SMRR Locking support
The SMRR MSRs can be locked, so that a further write to them will cause
a #GP.  This patch adds that functionality, but since the MSR is a
core-level register, it must only be done once per core; if the SoC has
hyperthreading enabled, then attempting to write the SMRR Lock bit on
the primary thread will cause a #GP when the secondary (sibling) thread
attempts to also write to this MSR.

BUG=b:164489598
TEST=Boot into OS, verify using `iotools rdmsr` that all threads have
the Lock bit set.

Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I4ae7c7f703bdf090144637d071eb810617d9e309
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45013
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kane Chen <kane.chen@intel.com>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-09-08 05:25:34 +00:00
Tim Wawrzynczak 4cba419676 soc/intel/common: Add SMRR Lock Supported bit definition for MTRR_CAP
The IA32_MTRR_CAP register has a bit which indicates that the SMRR MSRs
can be "locked" and this patch adds the definition for that.

BUG=b:164489598

Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I1254fb40c790f2a83dd11c2aabcf9bdf922b9395
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45012
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-09-08 05:25:14 +00:00
Tim Wawrzynczak 62669a24ea cpu/x86: Add definition for SMRR_PHYS_MASK_LOCK
The IA32_SMRR_PHYS_MASK MSR contains a 'Lock' bit, which will cause the
core to generate a #GP if the SMRR_BASE or SMRR_MASK registers are
written to after the Lock bit is set; this is helpful with securing SMM.

BUG=b:164489598

Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I784d1d1abec0a0fe0ee267118d084ac594a51647
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44991
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-09-08 05:24:42 +00:00
Jes Klinke 7f844ab8b7 mainboard/google/volteer: Disable S0i3.4 if cr50 firmware is too old
For Volteer (and future Tiger Lake boards) we can enable mode S0i3.4
only if we know that the Cr50 is generating 100us interrupt pulses.
We have to do so, because the SoC is not guaranteed to detect pulses
shorter than 100us in S0i3.4 substate.

A new Kconfig setting CR50_USE_LONG_INTERRUPT_PULSES controls new code
running in verstage, which will program a new Cr50 register, provided
that Cr50 firmware is new enough to support the register.

This CL adds code to detect the case when Cr50 is unable to generate
longer pulses, and in that case explicitly disable the S0i3.4 substate
as well as setting gpio_pm_override to all zeroes.  This will increase
power usage slightly, but guarantee that the GPIO block in the SoC
does not switch to a slower sampling clock.  In practice, this case
will only be encountered in the factory, before the Cr50 chip is
updated to a new RW image.

(Prior to this change, the gpio_pm_override was hardcoded to zero for
Volteer, but the S0i3.4 substate was not disabled.  According to my
conversations with Intel engineers, that was not enough to guarantee
detection pulses shorter than 100us.  But it is entirely possible that
we have just been "lucky" that the SoC has not gone into low power
mode during the boot process, where most of the cr50 communication
happens.)

TEST=util/abuild/abuild -t GOOGLE_VOLTEER -c max -x
BUG=b:154333137

Change-Id: Idef1fffd410a345678da4b3c8aea46ac74a01470
Signed-off-by: Jes Bodi Klinke <jbk@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44359
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-09-08 05:24:19 +00:00
Sumeet R Pawnikar 4fb3a40679 mb/intel/jasperlake_rvp: Add DTT support for jslrvp
Add DTT (Dynamic Tuning Technology) support for Jasper Lake based rvp board.
Set power limits and CPU sensor thresholds for DTT based thermal control.

BRANCH=None
BUG=Noe
TEST=Build and boot on jslrvp board

Change-Id: I41409c70d8472c54ca452fc98d5ee9edf3ccd307
Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44942
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-09-08 05:20:55 +00:00
CK Hu 80518ee512 soc/mediatek/mt8192: Add SPI flash controller DMA read function
To speed up SPI flash read, enable DMA read function.

Signed-off-by: CK Hu <ck.hu@mediatek.com>
Change-Id: Ic1679ef7940258350feeadac50ad8ea407fd7b90
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44851
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2020-09-08 02:14:49 +00:00
Kevin Chiu 2ee5dcb153 mb/google/kukui: Add LPDDR4X Samsung K4UBE3D4AA-MGCR 4GB support
Support 4GB Samsung K4UBE3D4AA-MGCR discrete DDR bootup.

BUG=b:162379736
BRANCH=kukui
TEST=emerge-jacuzzi coreboot

Change-Id: I2f4f084ece067e9884c23004506b450a281a77a6
Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45101
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-08 02:07:04 +00:00
Tony Huang bfb18e10bc hatch: Create dooly variant
Create the dooly variant of the puff reference board by copying
the template files to a new directory named for the variant.

(Auto-Generated by create_coreboot_variant.sh version 4.1.2).

BUG=b:155261464
BRANCH=puff
TEST=util/abuild/abuild -p none -t google/hatch -x -a
make sure the build includes GOOGLE_DOOLY

Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Change-Id: I8e714cc9bf4a49266da77db88f8c4a3ca45878d1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45026
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Reviewed-by: Sam McNally <sammc@google.com>
2020-09-08 00:42:12 +00:00