Instead of just printing the register contents, normalize the contents
of the base and limit registers to actual MMIO addresses and then print
those. This will hopefully avoid some confusion caused by the shifted
addresses.
Output on Mandolin before the patch:
=== Data Fabric MMIO configuration registers ===
Addresses are shifted to the right by 16 bits.
idx control base limit
0 93 fc00 febf
1 93 1000000 ffffffff
2 93 d000 f7ff
3 1093 fed0 fedf
4 90 0 0
5 90 0 0
6 90 0 0
7 90 0 0
Output on Mandolin after the patch:
=== Data Fabric MMIO configuration registers ===
idx control base limit
0 93 fc000000 febfffff
1 93 10000000000 ffffffffffff
2 93 d0000000 f7ffffff
3 1093 fed00000 fedfffff
4 90 0 ffff
5 90 0 ffff
6 90 0 ffff
7 90 0 ffff
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I62eeb88ddac6a7a421fccc8e433523459117976a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72739
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
This moves the definition for POST_BOOTBLOCK_CAR from the intel-specific
postcodes into the common postcode list, and uses it for the
cache-as-RAM init as needed.
Because POST_BOOTBLOCK_CAR was set to 0x20 in some spots and 0x21 in
most of the others, the values were consolidated into 0x21. This will
change the value on some platforms.
Any conflicts should get sorted out later in the conversion process.
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I8527334e679a23006b77a5645f919aea76dd4926
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71596
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
This patch enables PCIe port for WLAN as per mtlrvp schematics
BUG=b:224325352
BRANCH=None
TEST=Build and boot mtlrvp to ChromeOS. Ensure that WLAN module gets
is enumerated as part of lspci in AP console.
ae:00.0 Wireless controller [0d40]: Intel Corporation XMM7360 LTE
Advanced Modem (rev 01)
Signed-off-by: Harsha B R <harsha.b.r@intel.com>
Change-Id: Ief3c0eff40ced57d29ce343e569b6b392c27ad74
Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72778
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch enables EC_GOOGLE_CHROMEEC_SWITCHES for MTL_CHROME_EC which
helps in mode switch using dut-control power_state:rec.
BUG=b:224325352
BRANCH=None
Test=Able to build and boot MTLRVP to ChromeOS. Check if chroot command
dut-control power_state:rec puts the DUT to recovery mode.
Signed-off-by: Harsha B R <harsha.b.r@intel.com>
Change-Id: I5de0cd6c9a50bd85238205e09976a8bd8dd7142f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72813
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Usha P <usha.p@intel.com>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
This patch enables PCIe port for WWAN as per mtlrvp schematics
BUG=b:224325352
BRANCH=None
TEST=Build and boot mtlrvp to ChromeOS. Ensure that WWAN module
gets enumerated with cbmem -c.
\_SB.PCI0.RP07: Enable RTD3 for PCI: 00:1c.6 (Intel PCIe Runtime D3)
\_SB.PCI0.RP07: Enable WWAN for PCI: 00:1c.6 (Fibocom FM-350-GL)
Signed-off-by: Harsha B R <harsha.b.r@intel.com>
Change-Id: Ib372db9642a3c7b3a21a112fa0e6e0b4bc88a9ea
Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72777
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch adds ACPI support for Type-C ports.
BUG=b:224325352
BRANCH=None
Test=Able to build and boot MTLRVP. Verify SSDT for the corresponding
entry,
\_SB.PCI0.PMC.MUX.CON0 under Device (CON0)
\_SB.PCI0.PMC.MUX.CON1 under Device (CON1)
\_SB.PCI0.PMC.MUX.CON2 under Device (CON2)
\_SB.PCI0.PMC.MUX.CON3 under Device (CON3)
Signed-off-by: Harsha B R <harsha.b.r@intel.com>
Change-Id: I8e5957ca7a6c542a64d79b2ceefbed79ead15811
Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72789
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Usha P <usha.p@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Found-by: linter
Change-Id: I7c6d0887a45fdb4b6de294770a7fdd5545a9479b
Signed-off-by: Alexander Goncharov <chat@joursoir.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72795
Reviewed-by: Nicholas Chin <nic.c3.14@gmail.com>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Erik van den Bogaert <ebogaert@eltan.com>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
ELAN updated the datasheet, the HID/I2C protocol's T3 delay
time is 150ms now. Modify the kano's delay time to follow
the requiremnet.
BUG=b:247944006
TEST=Manually checked touchscreen works after reboot and suspend.
Change-Id: I42a7737060a82c0b27717f1510b8ec64abd1465a
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72784
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paz Zcharya <pazz@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Flashrom needs libgpiod-dev to build the new bitbanging programmer
driver for Linux libgpiod.
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I88f7e11fab115487cc44d4b89b3eab4745ad058d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72371
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Add extended capability ID for Address Translation Services. This
definition can be found in PCI Express Base Specification rev6.0
9.3.7.
Signed-off-by: Tim Chu <Tim.Chu@quantatw.com>
Change-Id: I777070ea223fc7e83c510c8eadbe4e028825eef6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71929
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Since the LIDS field is only used in the ACPI code and not in the C code
of any mainboard using the Glinda SoC, remove it form the global NVS.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I627d05c09d9637caf15e17285dd2c8e0389747c5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72187
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Since the LIDS field is only used in the ACPI code and not in the C code
of any mainboard using the Phoenix SoC, remove it form the global NVS.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I24ad0a2fbc5a973c0cb40ed10942b5efc31191aa
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72186
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Since the LIDS field is only used in the ACPI code and not in the C code
of any mainboard using the Mendocino SoC, remove it form the global NVS
and add an ACPI object for this in the DSDT of the mainboards that use
it in their ACPI code.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I1ed0407826f579eb14169246b7b14ba677c20e8d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72185
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Since the LIDS field is only used in the ACPI code and not in the C code
of any mainboard using the Cezanne SoC, remove it form the global NVS
and add an ACPI object for this in the DSDT of the mainboards that use
it in their ACPI code.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I6953da5e0f1966aa3022364d9a9c72ebafc698cc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72184
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Since the LIDS field is only used in the ACPI code and not in the C code
of any mainboard using the Picasso SoC, remove it form the global NVS
and add an ACPI object for this in the DSDT of the mainboards that use
it in their ACPI code.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ia265f3eebf5e48c185d2e4bf4ef74f8eab7c9606
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72183
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Since the LIDS field is only used in the ACPI code and not in the C code
of any mainboard using the Stoneyridge SoC, remove it form the global
NVS and add an ACPI object for this in the DSDT of the mainboards that
use it in their ACPI code. Eventually the LIDS object should probably be
moved to the EC's ACPI code, but that's out of scope for this patch.
TEST=google/liara doesn't show ACPI errors in Linux' dmesg
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I778c4189607035b4765c6cb8b2e74030dcf9069f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72182
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
This simplifies the code flow of the cpu init. APL can do CPU init after
calling FSP-S, while GLK needs to do that before. This is now reflected
directly in the cpu ops rather than using
CONFIG_SOC_INTEL_COMMON_BLOCK_CPU_MPINIT as a proxy.
Change-Id: I7fd1db72ca98f0a1b8fd03a979308a7c701a8a54
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72705
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
By default this limits PCI buses to CONFIG_MMCONF_BUS_NUMBER.
Some platforms have multiple PCI root busses (e.g. xeon_sp), where bus
numbers are limited. This provides a basic check. On some platforms it
looks like programming 0xff to the subordinate bus number confuses and
hangs the hardware.
Change-Id: I0582b156df1a5f76119a3687886c4d58f2d3ad6f
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59395
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
This patch removes the configuration of GPP_A12 for mtlrvp. Garfield
Peak (WLAN) doesn't use GPP_A12 for WAKE_N. Configuring GPP_A12 pin
prevents system entering G3 (reboots) on issuing shutdown -h now. Hence
configuring GPP_A12 as PAD_NC.
BUG=b:224325352
BRANCH=None
TEST=On issuing 'shutdown -h now' system enters G3
Signed-off-by: Harsha B R <harsha.b.r@intel.com>
Change-Id: I5e46b8afd3e0055440fd3c3db4aa5a9f1d4aa556
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72742
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Usha P <usha.p@intel.com>
This is to warn if a user add to Makefile a path to nonexistent
directory.
Change-Id: I5a30c3830f30509deaaadc6eaeab0e17bc08565c
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70251
Reviewed-by: Erik van den Bogaert <ebogaert@eltan.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
We don't need flashrom support just for vboot payloads. The current
default (USE_FLASHROM=1) is mostly harmless, especially if libflashrom
is not present (the autodetection in vboot_reference just spits out a
pkg-config error but doesn't actually fail the build), but it's better
to be clear we don't need it.
BUG=b:172225709
TEST=build
Change-Id: I53bcc2d1e7666646ddad58ba3717cfdd321014e8
Signed-off-by: Brian Norris <briannorris@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72716
Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
And make less levels of indentations in the code.
Change-Id: Ib8cae386eace4f423bde9c252992625e1ff3c690
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51881
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
1. Enable Cnvi BT Audio Offload feature and also
configure the virtual GPIO for CNVi Bluetooth I2S pads.
2. According to the SOC_GPIO_Table_20230116,
Change GPIO GPP_D15, GPP_D16 to NC.
BUG=b:264834572
TEST=FW_NAME=omnigul emerge-brya coreboot
Change-Id: I4901c8cd660f2d47018e4cccdb67f666f0800423
Signed-off-by: Jamie chen <jamie_chen@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72035
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
This variant was added without a devicetree, so add the board
specific devicetree according to schematic_20230110.
BUG=b:263060849
BRANCH=None
TEST=FW_NAME=omnigul emerge-brya coreboot
Change-Id: Ie05c152a20953e3e2d5f4ba5f9c00160a3e418e1
Signed-off-by: Jamie Chen <jamie_chen@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71883
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
NVMe PCIe 9-12 using clk_src1 and clk_req2 mapping to hardware design,
Due to inconsistency between PMC firmware and FSP, we need to set
clk_src to clk_req number, not same as hardware mapping in coreboot.
Then swap correct setting to clk_src=1,clk_req=2 in mFIT.
BUG=b:265720813
TEST=build firmware and veirfy suspend function on DUT.
Cq-Depend: chrome-internal:5351299
Change-Id: Ia057dfa98cb9293d9e212edb4e4ac198e94e8985
Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72051
Reviewed-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Turn off camera power during S0ix to improve power consumption.
BUG=b:265754302
BRANCH=firmware-brya-14505.B
TEST=emerge-brya coreboot chromeos-bootimage
Signed-off-by: Frank Chu <Frank_Chu@pegatron.corp-partner.google.com>
Change-Id: Ie2b300783adfc1cab30bc897d086a3674436724a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72089
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frank Chu <frank_chu@pegatron.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Add configuration to bump up the SPI flash bus speed from 66 MHz to 100
MHz starting the board version of the current phase.
BUG=b:260127676
TEST=Build and boot to OS in Frostflow with 100 MHz SPI bus speed.
Observe that the boot time improved by 100 ms compared to 66 MHz SPI
flash bus speed.
firmware log:
SPI fast read speed: 100 MHz
At 66 MHz:
Total Time: 1,563,384
At 100 MHz:
Total Time: 1,462,570
Change-Id: I9435f4ad0d3541b040703dc9a453badbd080dc09
Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72694
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Fix:
cc1: error: src/vendorcode/amd/pi/00670F00: No such file or directory [-Werror=missing-include-dirs]
cc1: error: src/vendorcode/amd/pi/00670F00/binaryPI: No such file or directory [-Werror=missing-include-dirs]
cc1: error: src/vendorcode/amd/pi/00670F00/Include: No such file or directory [-Werror=missing-include-dirs]
cc1: error: src/vendorcode/amd/pi/00670F00/Proc: No such file or directory [-Werror=missing-include-dirs]
cc1: error: src/vendorcode/amd/pi/00670F00/Proc/Common: No such file or directory [-Werror=missing-include-dirs]
cc1: error: src/vendorcode/amd/pi/00670F00/Proc/CPU: No such file or directory [-Werror=missing-include-dirs]
cc1: error: src/vendorcode/amd/pi/00670F00/Proc/CPU/Family: No such file or directory [-Werror=missing-include-dirs]
cc1: error: src/vendorcode/amd/pi/00670F00/Proc/Fch: No such file or directory [-Werror=missing-include-dirs]
cc1: error: src/vendorcode/amd/pi/00670F00/Proc/Fch/Common: No such file or directory [-Werror=missing-include-dirs]
Change-Id: I745f4fc421c91c413fe0d3155d3494ed9704eeb6
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71855
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
This allows the user to pass one or more arguments through the testsoc
script to abuild.
Example:
testsoc -K SOC_AMD_CEZANNE -a "--skip_unset BOARD_GOOGLE_NIPPERKIN"
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: Ic2bc8d656022560ed1eebf6eee0512d3633ebe84
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72766
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Not exactly sure about the usb4_xhci controllers, but for now I assume
those will behave like any other XHCI controller.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I22384f58e245a1486793831d29d22e9c618f646c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72773
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
The PCI Device ID Assignments table from PPRs #57019 Rev 1.65 and
PPR #57396 Rev 1.54 were used as a reference. Some devices will need to
have ops added in future patches. Since the xhci_2 device isn't there
any more, also drop it from the mainboard devicetrees. The actual USB
port configuration on xhci_0 and xhci_1 is updated in the next patch.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I49721bc44fa1e2a0118a8c3ac79a36aee64be687
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72771
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Now that the PCIe ports on device 1 are added, rename the aliases for
the PCIe ports on device 2 to have a common naming scheme. For phoenix
the device alias names are based on the device and function number the
bridge is connected to.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I5f5698408019bb9222b599dd78540ca1b187b56d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72737
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Only the PCIe ports on the functions of device 2 were present in the
devicetree and had the amd_external_pcie_gpp_ops ops assigned. Add the
missing PCIe ports on the functions of device 1 and assign the
amd_external_pcie_gpp_ops ops to them.
This SoC uses a slightly different naming scheme for its PCIe GPP ports.
Previously the PCIe GPP bridge number from the PCI Device ID Assignments
table from the PPR was used. Those bridge numbers are one less than the
function numbers of the device. This is due to function 0 being a dummy
bridge to avoid having to shuffle around the function numbers when the
first bridge is unused, since the PCIe specification mandates the
function 0 to be implemented if any other function on the same device is
implemented. In order for the device aliases to be consistent with the
PCIe device and function numbers which is way more commonly used and
also what lspci shows and what goes into the DXIO descriptors, change
the naming scheme of the aliases.
This was checked with PPR #57019 Rev 1.65 and PPR #57396 Rev 1.54.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ib5c62c1df585877d9b6986a462a3636d4f2eb4c7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72736
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This enables L1.2 for the SSD port.
link_hotplug is unused on Mendocino, so remove it while I'm here, just
as code cleanup. This has no functional difference.
Enabling L1.2 on other devices currently causes problems. Debug is
ongoing.
BUG=b:265890321
TEST=Build & boot, look at states enabled in lspci. Test device
functionality.
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I8940856a127c8a4ba45148cbbf07a08b621beb4d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72391
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
This patch requests FSP to enable the MRC fast boot feature along
with FSP v2473.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: If4a621e55c853505f7a702181ae5a70dc56d5b5a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72745
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch drops the WFC sensor OV8856 (reused from the Brya chassis)
support for Rex and added support for Rex specific UFC sensor OV13B10.
BUG=b:267264348
TEST=WFC MIPI cameras have been enabled using google/rex Proto 1.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Ic785b82db4368f40d91921f29c218cf417938541
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70226
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Enabling `SaGv` along with FSP v2473 is causing blank display issue.
Mostly likely we shouldn't enable SaGv yet on Intel MeteorLake.
BUG=b:267446159
TEST=Able to see ChromeOS UI in consecutive boot.
This reverts commit cbca81c594.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Ifbcc36515f7550c183c40e5af94684f5c3e39a7a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72774
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Reviewed-by: Jamie Ryu <jamie.m.ryu@intel.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Commit b171f76812 ("soc/amd/*: Hook up GPP bridges ops to devicetree")
missed adding the amd_external_pcie_gpp_ops ops to the gpp_gfx_bridge
PCIe ports, so add them. Those devices were previously covered by the
PCI_DID_AMD_FAM17H_MODEL60H_PCIE_GPP_D1 PCI device ID in the list that
got removed in the referenced commit.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I55434bf486569b32901b3840193a09cc5955abb2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72735
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
This switches the Picasso SoC to use the common reset code.
Picasso supports warm resets, so set the SOC_AMD_SUPPORTS_WARM_RESET
flag.
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I52515b20ef6c70b137f176d95480757b16bd8735
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72755
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This switches the Phoenix & Glinda SoCs to use the common reset code.
Cezanne and newer do not support warm reset, so use cold resets in all
cases (including the OS).
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I4593fa9766ac9e988722a02e355c971e147b8fae
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72754
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This switches the Cezanne & Mendocino SoCs to use the common reset code.
This patch does not change any behavior on those chips.
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: Ie05c790573e4e68f3ec91bacffcc7d7efb986d79
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72659
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This allows us to use the same file for PCO, CZN, MDN, PHX, & Glinda.
PCO supports the warm reset, and future chips can support it by setting
the SOC_AMD_SUPPORTS_WARM_RESET option.
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: Ib6459e7ab82aacbe57b4c2fc5bbb3759dc5266f7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72658
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
On family 15h and 16h processors with PSP, the PSP firmware type 0x5f
corresponds to AMD_FW_PSP_SMUSCS, while on family 17h and 19h this
corresponds to AMD_FW_TPMLITE. Add comments to those two enum values to
clarify this.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ia5c125ec6a0eb548f58a457f9040278391d2101c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72713
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Bao Zheng <fishbaozi@gmail.com>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Felix Held