Commit Graph

30532 Commits

Author SHA1 Message Date
Karthikeyan Ramasubramanian d06828da98 drivers/intel/wifi: Make Intel wifi driver arch agnostic
Mark Intel WiFi driver to depend on PCI and remove the dependency on x86
architecture.

BUG=None
BRANCH=None
TEST=Compile and Boot to ChromeOS.

Change-Id: I762007d53b43bbc78924ee8efe236d6a7ff4dc57
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33959
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-13 18:26:03 +00:00
Karthikeyan Ramasubramanian fd5d788f5e drivers/wifi: Add generic WiFi driver
Add generic WiFi driver to support common device operations across
multiple types of WiFi controller.

BUG=None
BRANCH=None
TEST=Boot to ChromeOS. Ensure that the SSDT table contains SAR tables
and wakeup GPE information. Ensure that the SSDT table is same after the
change.

Change-Id: Ica5edf95a37c8ed60f7e159d94fd58af5d41c0ef
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33155
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-07-13 18:25:47 +00:00
Furquan Shaikh 328c8bbd23 mb/google/hatch: Fix trackpad configuration in overridetree
Hatch and variants use GPP_A21 for trackpad IRQ and wake. Fix
overridetree.cb to advertise the right IRQ.

Change-Id: Ib87c858b89e8726c3bc80f83be0729ef4625268e
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34248
Reviewed-by: Philip Chen <philipchen@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-13 18:22:05 +00:00
Seunghwan Kim 0921962e44 mb/google/octopus: Add custom SAR values for Bluebird
Bluebird needs to use different SAR values than Casta.
Bluebird sku id is 2.

CQ-DEPEND=CL:*1435310
BUG=b:129725065
BRANCH=octopus
TEST=build

Change-Id: I107a8519832fcf906b94f958a3dc508d19bb4727
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34080
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-13 18:21:09 +00:00
Kyösti Mälkki 7fbed223c7 intel/i945: Fix udelay() prototypes
Change-Id: Ia157c6417bdd9c4ffbdf07683c51d0680e9356c9
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34228
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2019-07-13 17:58:01 +00:00
Kyösti Mälkki 3b50c05bb2 intel/haswell: Replace monotonic timer
Remove implementation of 24 MHz clock, available only
on Haswell ULT SKUs. Use TSC_MONOTONIC_TIMER instead
for all boards.

Change-Id: Ic4aeb084d1b0913368f5eaa46e1bd68411435517
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34114
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-07-13 17:56:32 +00:00
Elyes HAOUAS 8b9a3ec93a soc/rockchip/rk3288/include/soc: Add missing include <types.h>
Change-Id: Ibde48d7cff582c91f55ad5f1328aac64d018b3c5
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34235
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-13 17:55:51 +00:00
Elyes HAOUAS 237f1789e3 soc/qualcomm: Remove unneeded '#include <lib.h>'
Change-Id: I39db73014c0a4456750210c002787abf9bc79fce
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34232
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-07-13 17:55:21 +00:00
Martin Roth 3c2e287b7c console/Kconfig - only print UART addresses for I/O based UARTs
It doesn't make sense to print these values for memory-mapped UARTs.

Change-Id: Ie2d9cf95f0b0fdcf601e74de799b1390c08f2335
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34247
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-07-13 17:53:22 +00:00
Julius Werner f6410baaab fit_payload: Always set DT size
CB:32870 changed FIT loading code to make an FDT mandatory (because the
platforms that can use FIT images always need an FDT). Remove one
left-over conditional that is now dead code.

Found by Coverity.

Change-Id: Ia7765d45f068ab4bdc720ea7ae87dcc62a4b7d3d
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34224
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-07-13 16:15:16 +00:00
Aamir Bohra 8a77454e33 soc/intel/cannonlake: Remove unused header files from southbridge.asl
Change-Id: I1f970db22f87e8eba0129ca049f75d16539644a5
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34270
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2019-07-13 13:59:36 +00:00
Kyösti Mälkki b4905625eb soc,southbridge/intel: Avoid preprocessor with HAVE_SMI_HANDLER
Change-Id: Id375999adad71d95d4968398e90bc3c07f65ea83
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34254
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-13 13:22:15 +00:00
Kyösti Mälkki 09e2f6e1ba intel/fsp_rangeley: Avoid preprocessor with HAVE_SMI_HANDLER
Change-Id: Id9abc239a92fa7d3e29738f08f2ccdaf3232dfb6
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34253
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-07-13 13:19:53 +00:00
Kyösti Mälkki d1c1c9a76e drivers/elog: Fix ELOG_GSMI dependency
SMM_TSEG is a qualifier between TSEG and ASEG only, while
HAVE_SMI_HANDLER currently tells if SMM will be installed.

Move rest of the file under same 'if ELOG' block.

Change-Id: I620d3ce5aa9632d862d6480922144f002cf6423b
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34195
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-13 13:18:43 +00:00
Kyösti Mälkki d4e140dae7 cpu/x86: Move smm_lock() prototype
The function implementations are in local platform
scopes.

Change-Id: I7a3025398b15fe6d2c5a13cdb65f3e62a49c0bc6
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34151
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-13 13:17:21 +00:00
Kyösti Mälkki 55b7263ed8 intel/e7505,i82801dx: Fix SMM_ASEG lock
In our codebase, this is only coupled with intel/e7505.
The PCI registers reference here were for intel/i945.

Also aseg_smm_lock() was previously not called.

Change-Id: I21d991c8c2f5c2dde1f148fd80963e39d9836d3c
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34149
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-13 13:16:26 +00:00
Paul Menzel 3555389a8c payloads: Update GRUB stable from 2.02 to 2.04
GRUB 2.04 was released on July 5th, 2019, so update. The only change-log
is the git history. Some coreboot related changes are listed below.

1.  coreboot: Changed cbmemc to support updated console format from
    coreboot.
2.  ahci: Increase time-out from 10 s to 32 s
3.  normal/menu: Do not treat error values as key presses

When building from the git repository, `./bootstrap.sh` needs to be run
to set up Gnulib. Ignore the exit code, as older versions might not have
this script.

Change-Id: Iab0b87164ed86f15d3415af935998b59e0d76c45
Signed-off-by: Pablo <42.pablo.ms@gmail.com>
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34104
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-07-13 12:58:24 +00:00
Nico Huber 8417485f95 soc/intel/cnl: Sync CONFIG_LPSS_UART_FOR_CONSOLE with FSP
We got rid of the dangerous reconfiguration of arbitrary pads in
coreboot, but FSP still overrode that. Make sure that it doesn't
enable a UART for debug output when it isn't configured in core-
boot.

This, again, shows how dangerous it is to leave any FSP UPD at
its binary default.

Change-Id: I7280a80f71ddddbe78352eb696e6f5844d2df0b2
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34167
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-07-13 12:47:48 +00:00
Jacob Garber 0c4ed4bd7e arch, include, soc: Use common stdint.h
There are only minimal differences between the architecture specific
stdint.h implementations, so let's tidy them up and merge them together
into a single file. In particular,

- Use 'unsigned long' for uintptr_t. This was already the case for x86
  and riscv, while arm and mips used 'unsigned int', and arm64 and ppc64
  used 'unsigned long long'. This change allows using a single integer
  type for uintptr_t across all architectures, and brings it into
  consistency with the rest of the code base, which generally uses
  'unsigned long' for memory addresses anyway. This change required
  fixing several assumptions about integer types in the arm code.
- Use _Bool as the boolean type. This is a specialized boolean type that
  was introduced in C99, and is preferrable over hacking booleans
  using integers. romcc sadly does not support _Bool, so for that we
  stick with the old uint8_t.
- Drop the least and fast integer types. They aren't used
  anywhere in the code base and are an unnecessary maintenance burden.
  Using the standard fixed width types is essentially always better anyway.
- Drop the UINT64_C() macro. It also isn't used anywhere and doesn't
  provide anything that a (uint64_t) cast doesn't.
- Implement the rest of the MIN and MAX numerical limits.
- Use static assertions to check that the integer widths are correct.

Change-Id: I6b52f37793151041b7bdee9ec3708bfad69617b2
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34075
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-07-12 17:40:24 +00:00
Elyes HAOUAS 276d46ac05 src: Add missing include <device/pci_ops.h>
Change-Id: Iae73fc1557fb310dacbbf8bc486dc3cc5249d9e7
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33526
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-12 17:10:56 +00:00
Mario Scheithauer 56352e1f80 mb/siemens/mc_apl3: Enable LPSS UART 1
By setting the GPIOs 42 and 43 to native function 1 the LPSS UART 1 is
activated.

Change-Id: I74abd1b6fb5459cf11a5bdee182c99462f613b7a
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34238
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2019-07-12 17:09:21 +00:00
Elyes HAOUAS b14f3b8b0b vendorcode/amd/agesa/f15tn: Fix condition that has identical branches
This fixed function is never used.

Change-Id: Ia004756a0b301278f813067ab0ea580c5ea837d3
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34225
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-12 17:05:30 +00:00
Maxim Polyakov aae7552b24 util/superiotool/aspeed: fix SUART number
Change-Id: I20c4436d414bc6b9a3ff5138d6fd59ead8fd4a47
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34237
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2019-07-12 12:27:45 +00:00
Werner Zeh ac14a40d0e util/sconfig: Fix compile error with older glibc-headers
In patch e29a6ac16a (util/sconfig: Add
commonlib/helpers.h) helpers.h has been added to the include-list.
In headers.h we have a definition for __unused:

On a host system environment where glibc-headers-2.12-1.212 is
installed, a file included by <sys/stat.h> called bits/stat.h have the
following content on line 105 and onwards:

	long int __unused[3];
where the mentioned part is part of the structure called struct stat.

If we include commonlib/helpers.h _before_ <sys/stat.h>, the symbol for
__unused will be defined by the preprocessor to be
'__attribute__((unused))', therefore the above mentioned structure member
will be expanded by the preprocessor to be
'long int __attribute__((unused))[3];', which is not a valid C syntax
and therefore produces a compile error for sconfig tool.

To handle this case we need to make sure commonlib/helpers.h is included
_after_ <sys/stat.h>. As the needed part of stat.h (which is
struct stat) is only used in main.c it is safe to move the include from
sconfig.h directly into main.c while taking care of the order.

Change-Id: I9e6960a318d3dd999e1e9c1df326d67094f3b5ce
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34236
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-07-12 11:02:29 +00:00
Kyösti Mälkki 98d19572b1 device/oprom: Replace uses of dev_find_slot()
The call to dev_find_slot() may return PCI devices that
are disabled or unaccessible, as PCI enumeration does
not remove nodes from all_devices linked list.

Use PCI topology search instead.

Change-Id: I00233177e5572ca79002a7d141cda1b94b966330
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34083
Reviewed-by: Mike Banon <mikebdp2@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-12 09:27:56 +00:00
Nico Huber e2f39e23e8 pci_ids: Drop a block of unused, redundant definitions
These didn't align with the usual naming conventions and contained some
errors beside.

Change-Id: I45033d4cb998a85fc0bec00c54e207226f42de4e
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34209
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-07-12 08:58:28 +00:00
Nico Huber ff3c9647c3 soc/intel/common: Add Coffee Lake H 6+2 Xeon graphics id
Change-Id: Ibf72a8db2e4292e5d5bb67b8778e1d1ebfa19632
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34164
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-12 08:57:59 +00:00
Nico Huber 129bc4c0e0 soc/intel/common: Add CM246 LPC device id
Change-Id: Ic57ccf48988afbbba256172a7540bb02b88d1bbd
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34163
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-12 08:57:07 +00:00
Kyösti Mälkki ab275f0915 device/pci: Declare pcidev_path_on_bus()
It is recommended to never reference PCI busses
using a static number. There is exception with
OPROM execution, where we want to translate the
bus number captured from the actual IO operation
into a matching device node in the devicetree.

Change-Id: I733c645ac5581c000b4cd6cdc05829cd039324d5
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34077
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-07-12 08:52:50 +00:00
Kyösti Mälkki c19d6a6ce5 device/pci: Replace use of dev_find_slot() for IRQs
Change-Id: I48c0de73338430282ce1a4442bbeb7c867dc174c
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34079
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-07-12 08:52:22 +00:00
Subrata Banik 8da51ca2c3 Kconfig: Remove HAVE_RAMSTAGE dependency from RELOCATABLE_RAMSTAGE
CONFIG_RELOCATABLE_RAMSTAGE is something more than ramstage specific
kconfig hence its better to remove HAVE_RAMSTAGE dependency
till stage_cache cleaner implementation lands here.

Change-Id: I3c238d727dc13014e2b77544d05099be95c22bab
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34198
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-07-12 02:22:27 +00:00
Kyösti Mälkki b16fda22a4 cpu/x86: Declare smi_release_lock() static
Change-Id: I535ff1b16b1fa7c3c8c14b2be7eac32568f16077
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34194
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-11 21:03:37 +00:00
Rizwan Qureshi e211b9ed59 mb/google/hatch: Update AC/DC loadline values
Update the AC/DC loadline values for all domains. Using the same
values as in arcada.

BUG=None
BRANCH=None
TEST=Build and Boot hatch EVT

Change-Id: If8ea48794d11dc68e40e6504c0d46a2b273a8ab6
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33371
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-07-11 19:22:42 +00:00
Angel Pons b62c1e392b mb/asus/p8h61-m_pro: Add comment about PCH GPIO46
GPIO46 is wired to a tiny switch on the board labelled "GPU Boost".
Since coreboot could make use of it, add a comment about it on gpio.c.

Change-Id: I0efa85e6d8235711521b10e56b7c89a25c4b2b7f
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34185
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2019-07-11 15:15:20 +00:00
Mario Scheithauer 6c7857411c mb/siemens/{baseboard,mc_apl3,mc_apl4,mc_apl5}: Fix GPIO_168
This GPIO is corrected with reference to the Apollo Lake SoC EDS Vol 4
revision 2.4 chapter 10.1.2.3 List of Pins that are GPIOs but cannot be
used in Function 0 (GPIO) mode.

Change-Id: I98628ade3a1e19730ca6e6b4a63c28e6816176ce
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34197
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2019-07-11 15:14:32 +00:00
Mario Scheithauer 1f21a96c84 mb/siemens/{mc_apl1,...,mc_apl5}: Reduce eMMC bus speed mode
We need to reduce the eMMC bus speed for these Apollo Lake mainboards
because of a limitation on Intel side for industry use cases.

Change-Id: Ide6a1a302001c0752d149bfdab175a27c8f8cc35
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34196
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2019-07-11 15:14:06 +00:00
Yu-Ping Wu badbcde542 google/kukui: Adjust LCM ID voltages
Currently some of the LCM ID voltage gaps are below 100mV. For example, the
voltage difference between ID 2 and 3 is 503-440=63mV. To reduce the risk of
misrecognition from the hardware level, the voltages are adjusted so that all
the voltage gaps are larger than 100mV. The RD2 resistor values are also
updated.

BUG=b:136987483
TEST=emerge-kukui coreboot

Change-Id: Ib5c1f927fb54d8c9579f030e42eeec5a27daaceb
Signed-off-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34192
Reviewed-by: You-Cheng Syu <youcheng@google.com>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-11 15:11:06 +00:00
Tristan Shieh e13a65c5ff mediatek: Fill in input_hertz to coreboot table
Set input_hertz to 26 MHz.

BUG=b:134351649
BRANCH=none
TEST=emerge-kukui coreboot; emerge-elm coreboot

Change-Id: I7f9c329ae5d610f2516e60f06b2ac96ebbeaa897
Signed-off-by: Tristan Shieh <tristan.shieh@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34191
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2019-07-11 15:10:03 +00:00
Hung-Te Lin 447badd1cf board/kukui: Remove ADC tolerance from boardid
The tolerance of ADC is +-10mV, but the resistors may also
introduce 1% variation, and causing the final measured
voltage to vary around 5%.

By the advisory from hardware team, checking the tolerance
seems not really solving or helping anything so we should
just ignore that and try to find best matched ID (this
also aligns to what Gru did).

BUG=b:136990271
TEST=Booted on Krane and no longer seeing ADC out of range
BRANCH=None

Change-Id: Ie02ca5aaafbcfa8f411d973ad0266eee385d6878
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34161
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: You-Cheng Syu <youcheng@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-11 15:09:05 +00:00
T Michael Turney ff423f749a sdm845: Add AOP firmware support
TEST=build & run

Change-Id: I9845c8638e4b905de5d6985dc9f1fddd8b1a8942
Signed-off-by: T Michael Turney <mturney@codeaurora.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/25210
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-11 15:08:38 +00:00
Frank_Chu 125b48d1d5 mb/google/hatch/variants: Fix nonworking touch pad
Correct ELAN Touch pad IRQ GPIO to GPP_A21

BUG=b:135507215
BRANCH=none
TEST=emerge-hatch coreboot chromeos-ec chromeos-bootimage

Signed-off-by: Frank_Chu <frank_chu@pegatron.corp-partner.google.com>
Change-Id: I60816a4652fa39ab2a91034b268efe8f84a13e17
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33954
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-11 15:05:47 +00:00
Tim Wawrzynczak c5651568ea mb/google/hatch: Enable/disable GPIO clock gating
Before the system enters S0ix or S3, each GPIO community
will have its dynamic clock gating turned on.  Upon return
to S0, the dynamic clock gating will be turned back off.

BUG=b:130764684
BRANCH=none
TEST=Used dut-power to verify that the clock gating is enabled
in S0ix and S3.  Also used Store(..., Debug) statements in the
ASL code to verify it was getting called.

Change-Id: I20ff2aac035eaa5912af6c946d837567a4918bbf
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34180
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-07-11 15:03:09 +00:00
Tim Wawrzynczak a17242577a soc/intel/cannonlake: Add GPID and CGPM methods to GPIO ASL
The GPID method returns the PCR Port ID of the given GPIO community.
The CGPM method alters the given GPIO community's PM bits, given in
Arg1.

Change-Id: I098ee08573eb4f8a45d9b5ae84f2d85ce525c9b8
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34179
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-07-11 15:02:43 +00:00
Tim Wawrzynczak 69d73e4d75 soc/intel/intelblocks/gpio: Always expose GPIO PM constants
These constants are needed in some ASL files, even when
__ACPI__ is defined.

Change-Id: I0f4f00b93d5d45794b7c9e0f72b51f3191eb3902
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34177
Reviewed-by: Lance Zhao <lance.zhao@gmail.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-11 15:02:18 +00:00
Tim Wawrzynczak 489c722dcc mb/google/hatch: Enable LPIT inclusion in DSDT
Include the lpit.asl file in Hatch's DSDT definition.

BUG=b:130764684
BRANCH=none
TEST=S3 suspend/resume and S0ix entry/exit work correctly.
Ran > 200 iterations of suspend_stress_test and no issues found.

Change-Id: If8ebff3db091257e8452869636c0e024f3123e8b
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34175
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
2019-07-11 15:01:59 +00:00
Tim Wawrzynczak 145748bf25 mb/google/hatch: Disable GPIO community dynamic clock gating
The dynamic clock gating is causing boards to miss interrupts
whose pulses are shorter than 4us.  Disable it using FSP UPDs.

BUG=b:130764684
BRANCH=none
TEST=Compiles

Change-Id: I8f1ec8f7c31192bce2a761ec99b86638435dc27c
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34176
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Evan Green <evgreen@chromium.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2019-07-11 15:01:41 +00:00
Tim Wawrzynczak 20cfc87ca0 soc/intel/cannonlake: Make EC S0ix notification optional in LPIT
Only call the \_SB.PCI0.LPCB.EC0.S0IX method if it exists.

Change-Id: Idf465f8ad7cb016f3ad3d9710b46e35f66f8939b
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34178
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Shaunak Saha <shaunak.saha@intel.com>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2019-07-11 15:01:24 +00:00
Lean Sheng Tan 565b0aada9 mb/intel/coffeelake_rvp: Add cpu count for CFL S62
Increases CPU max core count to 16 for coffeelake Refresh-S Platform.

TEST: boot to linux OS on CFL-S refresh Intel RVP and verified the output
     of cat /proc/cpuinfo shows no of processor=16.

Signed-off-by: Lean Sheng Tan <lean.sheng.tan@intel.com>
Change-Id: I579ff6ae8227844741406c503d3994408ec2b617
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34156
Reviewed-by: Boon Tiong Teo <boon.tiong.teo@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-11 15:00:49 +00:00
John Zhao 1ceac4efcf soc/intel/common: Check bios_size and window_size after MIN operation
Clang Static Analyzer version 8.0.0 detects that the result of
log2_ceil(bios_size) and log2_ceil(window_size) is undefined if the
value of bios_size and window_size are negative. Add negative value
Check for bios_size and window_size after MIN operation.

Change-Id: I28577b6e0ba0ab45bb7804c17ba1f26c4b078b15
Signed-off-by: John Zhao <john.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34182
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2019-07-11 15:00:13 +00:00
Furquan Shaikh b8501c7c5f mb/google/hatch: Fix interrupt trigger type for GPP_H0(HP_INT_L)
HP_INT_L(GPP_H0) is configured for GPIO IRQ instead of APIC IRQ since
it needs to trigger on both edges. With GPIO IRQ, it is necessary to
configure the trigger type in coreboot to match the ACPI
configuration. This is because:
1. ACPI configuration is used by intel-pinctrl driver in Linux kernel
to re-configure the trigger type for the pad in GPIO DW0 config
register. This is done when kernel driver probes and requests irq for
its device.
2. On resume from S3, the pad configuration gets reset and coreboot
sets the trigger type to LEVEL. However, kernel driver does not probe
again. This results in the trigger type being configured incorrectly.

This change updates the GPIO configuration for GPP_H0 to set the same
trigger type as advertised in ACPI for the kernel.

BUG=b:132672011
TEST=Verified that S3 works fine. Verified that interrupt on GPP_H0
works fine on boot as well as after suspend/resume.

Change-Id: Ieb44c7403a2f4911b4a8f422053dee8bcfb91d85
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34181
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Sathya Prakash M R <sathya.prakash.m.r@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-11 06:01:15 +00:00