Commit Graph

19281 Commits

Author SHA1 Message Date
Hannah Williams 4cff1d52a5 soc/intel/common/acpi: Add _PTS, _WAK methods
Change-Id: I72f894fd14bf0e333d9fda970397a3c82de598c3
Signed-off-by: Hannah Williams <hannah.williams@intel.com>
Reviewed-on: https://review.coreboot.org/15121
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-22 17:26:15 +02:00
Kyösti Mälkki cf0e60faf4 ACPI S3: Add common recovery code
There is nothing to backup with RELOCATABLE_RAMSTAGE.

Change-Id: I780a71e48d23e202fb0e9c70e34420066fa0e5b5
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/15243
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-22 12:10:17 +02:00
Kyösti Mälkki 8e627a2e51 ACPI S3: Fix prohibited wakeup
No boards affected, resume is always allowed when enabled
in the build.

Change-Id: I1816557da8201af9e137c389b57852ec20390b6a
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/15275
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-22 12:07:53 +02:00
Kyösti Mälkki d132c996a6 ACPI S3: Split support for HAVE_ACPI_RESUME
Some of the support functions will be built for romstage
once HIGH_MEMORY_SAVE is removed.

Change-Id: I43ed9067cf6b2152a354088c1dcb02d374eb6efe
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/15242
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-22 12:04:25 +02:00
Kyösti Mälkki 34fcec1933 cpu/cpu.h: Change guard around function declarations
This file is pulled for x86 bootblock builds using ROMCC,
which would choke on struct bus.

Change-Id: Ie3566cd5cfc4b4e0e910b47785449de81a07b9ef
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/15274
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-06-22 11:40:09 +02:00
Kyösti Mälkki a16cd9cdda ACPI S3: Move SMP trampoline recovery
No need to make low memory backup unless we are on
S3 resume path.
Hide those details from ACPI.

Change-Id: Ic08b6d70c7895b094afdb3c77e020ff37ad632a1
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/15241
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-22 11:31:35 +02:00
Kyösti Mälkki 65cc526f6f Ignore RAMTOP for MTRRs
Without RELOCATABLE_RAMSTAGE have WB cache large enough
to cover the greatest ramstage needs, as there is no benefit
of trying to accurately match the actual need. Choose
this to be bottom 16MiB.

With RELOCATABLE_RAMSTAGE write-back cache of low ram is
only useful for bottom 1MiB of RAM as a small part of this gets used
during SMP initialisation before proper MTRR setup.

Change-Id: Icd5f8461f81ed0e671130f1142641a48d1304f30
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/15249
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-22 11:03:42 +02:00
Kyösti Mälkki c5400efc11 intel: Drop old romstage main() without asmlinkage
Change-Id: I0d471766fdf46f6e61ac692fc98730a2429f981f
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/15234
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-22 10:53:17 +02:00
Kyösti Mälkki 75d139bdf2 intel/model_206ax: Prepare for dynamic CONFIG_RAMTOP
Change-Id: Ib3250677ee926deaa957c83aca7479eb0159358c
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/15231
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-22 10:50:51 +02:00
Kyösti Mälkki 8431fcb8c8 intel/model_2065x: Prepare for dynamic CONFIG_RAMTOP
Change-Id: I616143b55d7c5726dc2475434e3fcb08b8d69bda
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/15230
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-22 10:49:18 +02:00
Kyösti Mälkki b4f827d45a intel cache-as-ram: Fix comment about MTRRs
Change-Id: I5b9e10fe119c1a046494235e85f730bedfe8578d
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/15282
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-22 10:48:18 +02:00
Douglas Anderson e00b2de71c rockchip: kevin/gru: Slow memory down to 300 MHz
At the higher speeds stressapptest shows memory errors.  We don't want
to track down random problems due to simple memory corruption, so slow
memory back down to 300 MHz until someone figures out how to make it
faster without sacrificing reliability.

BRANCH=None
BUG=chrome-os-partner:54144
TEST=stressapptest -M 1024 -s 240

Change-Id: I2417f93f65b1491a028a63ce563ed7dd7831becc
Signed-off-by: Martin Roth <martinroth@chromium.org>
Original-Commit-Id:
Original-Change-Id: I02182b25e677e27e8541445938f9da9ae9553fa6
Original-Signed-off-by: Douglas Anderson <dianders@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/350480
Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://review.coreboot.org/15120
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-06-21 22:52:32 +02:00
Lin Huang 9a5c4fefec rockchip: gru: pass poweroff gpio parameter to BL31
To support gpio power off SOC, we need to pass the power off
gpio parameter to BL31. Gru reuse tsadc overtemp pin as power
off gpio, so need to iomux to gpio function when use gpio power
off function, either in bl31 or depthcharge.

BRANCH=None
BUG=chrome-os-partner:53448
TEST=Build gru

Change-Id: Ibfe64042f39f6df1b87536b50fe432859bf74426
Signed-off-by: Martin Roth <martinroth@chromium.org>
Original-Commit-Id:
Original-Change-Id: Ie7a1bbea4a12753f0abac7a9142f2e032686ce31
Original-Signed-off-by: Lin Huang <hl@rock-chips.com>
Original-Signed-off-by: Douglas Anderson <dianders@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/349703
Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://review.coreboot.org/15119
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-06-21 22:50:28 +02:00
Lin Huang 5a4be8a2c7 rockchip: gru: pass reset gpio parameter to BL31
To support gpio reset SOC, we need to pass the reset gpio
parameter to BL31. Note: request BL31 have supported this
function.

BRANCH=None
BUG=chrome-os-partner:51924
TEST=Build gru

Change-Id: I182cff11ce6f5dc3354db0dc053c128b813acf9f
Signed-off-by: Martin Roth <martinroth@chromium.org>
Original-Commit-Id:
Original-Change-Id: I8283596565d552b1f3db31c28621a1601c226999
Original-Signed-off-by: Lin Huang <hl@rock-chips.com>
Original-Signed-off-by: Douglas Anderson <dianders@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/349702
Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://review.coreboot.org/15118
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins)
2016-06-21 22:37:02 +02:00
Lin Huang 8f1f982565 rockchip: gpio: add macro so we can get gpio number
sometimes we need gpio number, so add this macro so we
can get the gpio number if we need.

BRANCH=None
BUG=chrome-os-partner:51924
TEST=Build gru

Change-Id: I0c8c6cc0643a66e9ae1f21b02c7364c641b9805d
Signed-off-by: Martin Roth <martinroth@chromium.org>
Original-Commit-Id:
Original-Change-Id: I98e8cf15543179904295a86e9f720c2d7c8b443a
Original-Signed-off-by: Lin Huang <hl@rock-chips.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/349701
Original-Commit-Ready: Douglas Anderson <dianders@chromium.org>
Original-Tested-by: Douglas Anderson <dianders@chromium.org>
Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://review.coreboot.org/15117
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-06-21 22:25:29 +02:00
Furquan Shaikh e0667f7b54 google/reef: Keep ISH enabled for now
Disabling ISH causes resets in FSP which leads to hang. This should be
fixed in a later stepping. Until then keep ISH enabled.

BUG=chrome-os-partner:54033

Change-Id: Id9cb276eed8d027ab6d2e81a5ec962bc730c1ff5
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/15142
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
2016-06-21 22:01:55 +02:00
Furquan Shaikh 49f7dd9982 libpayload/pci: Correct MASK macro names
BUG=chrome-os-partner:54563

Change-Id: I8ef1c595205fe46dd64357051eeb232e2bbbebc1
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/15270
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-06-21 20:41:06 +02:00
Furquan Shaikh 0be3da53c6 intel/apollolake: Calculate BIOS mmap at runtime
Instead of hard-coding the BIOS region start and end addresses, read
BIOS_BFPREG to determine the base and limit for the mapped BIOS
region.

BUG=chrome-os-partner:54563

Change-Id: Iddd3d4cc945f09e8f147e293bb9144471a6a220d
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/15269
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
2016-06-21 20:39:32 +02:00
Furquan Shaikh bdcda710a7 intel/apollolake: Add helper routine for spi reg read
BUG=chrome-os-partner:54563

Change-Id: I56bc6b5292aec676103a436048abee8577edd961
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/15268
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-21 20:38:15 +02:00
Furquan Shaikh d3f4c5be8b intel/apollolake: Rename _spi_reg_read/write to _spi_ctrlr_read/write
This makes it clearer that the read/write operations are being performed
on the host controllers registers.

Change-Id: Id63d778a4a03c461d97e535c34b85ada3ae469de
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/15281
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-21 20:25:28 +02:00
Furquan Shaikh 2b57691ce0 commonlib/region: Add helpers for dynamic initialization of region dev
This allows initialization of runtime region devices and xlate region
devices where all parameters cannot be statically determined.

BUG=chrome-os-partner:54563

Change-Id: Ia6e1b695fed3bbfa08598d1593e650fc1465d41f
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/15267
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-21 20:23:40 +02:00
Furquan Shaikh f4dac8ac06 commonlib/region: Rename XLATE region device init macro
This makes the name consistent with other region device init macros.

Change-Id: I248894ba6c85326b615dcb71e8f498bc8be50911
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/15277
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-21 20:09:34 +02:00
Furquan Shaikh bae6383607 intel/apollolake/spi: Add support for reading status reg
spi_read_status reads the status register using hardware sequencing and
returns 0 on success and -1 on error. Use spi_read_status to return
appropriate value for get_sw_write_protect.

BUG=chrome-os-partner:54283

Change-Id: I7650b5c0ab05a8429c2b291f00d4672446d86e03
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/15266
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-21 20:04:33 +02:00
Furquan Shaikh cad9b63136 intel/apollolake: Disable setting of EISS bit in FSP
chrome-os-partner:54589

Change-Id: I5bdd417ed2f7ec013aeb8a0d4a9de57b1ad564a1
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/15276
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-21 19:57:48 +02:00
Furquan Shaikh bd205419f1 intel/skylake: Run spi_init as early as possible in ramstage
spi_init should be run early enough in ramstage so that any init
calls (e.g. mainboard_ec_init) that write on flash have right
permissions set.

Change-Id: I9cd3dc723387757951acd40449d4a41986836d2a
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/15235
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-06-21 19:54:23 +02:00
Furquan Shaikh 6ac226d915 intel/apollolake: Enable SPI properly in bootblock and ramstage
Bootblock:
   - Temporary BAR needs to be assigned for SPI device until PCI
   enumeration is done by ramstage which allocates a new BAR.
   - Call spi_init to allow bootblock/verstage to write/erase on flash.

Ramstage:
   - spi_init needs to run in ramstage to allow write protect to be
   disabled for eventlog and NVRAM updates. This needs to be done pretty
   early so that any init calls(e.g. mainboard_ec_init) writing to flash
   work properly.

Verified with this change that there are no more flash write/erase
errors for ELOG/NVRAM.

BUG=chrome-os-partner:54283

Change-Id: Iff840e055548485e6521889fcf264a10fb5d9491
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/15209
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
Tested-by: build bot (Jenkins)
2016-06-21 19:52:25 +02:00
Duncan Laurie 88a1f14cad lpss_i2c: Set SDA hold and support custom speed config
This I2C controller has separate registers for different speeds to set
specific timing for SCL high and low times, and then a single register
to configure the SDA hold time.

For the most part these values can be generated based on the freq of
the controller clock, which is SOC-specific.  The existing driver was
generating SCL HCNT/LCNT values, but not the SDA hold time so that is
added.

Additionally a board may need custom values as the exact timing can
depend on trace lengths and the number of devices on the I2C bus. This
is a two-part customizaton, the first is to set the values for desired
speed for use within firmware, and the second is to provide those
values in ACPI for the OS driver to consume.

And finally, recent upstream changes to the designware i2c driver in
the Linux kernel now support passing custom timing values for high
speed and fast-plus speed, so these are now supported as well.

Since these custom speed configs will come from devicetree a macro is
added to simplify the description:

register "i2c[4].speed_config" = "{
	 LPSS_I2C_SPEED_CONFIG(STANDARD, 432, 507, 30),
	 LPSS_I2C_SPEED_CONFIG(FAST, 72, 160, 30),
	 LPSS_I2C_SPEED_CONFIG(FAST_PLUS, 52, 120, 30),
	 LPSS_I2C_SPEED_CONFIG(HIGH, 38, 90, 30),
}"

Which will result in the following speed config in \_SB.PCI0.I2C4:

Name (SSCN, Package () { 432, 507, 30 })
Name (FMCN, Package () { 72, 160, 30 })
Name (FPCN, Package () { 52, 120, 30 })
Name (HSCN, Package () { 38, 90, 30 })

Change-Id: I18964426bb83fad0c956ad43a36ed9e04f3a66b5
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/15163
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-21 19:32:24 +02:00
Benjamin Barenblat 9993286de2 payloads/external/GRUB2: Pass CONFIG_GRUB2_EXTRA_MODULES
Set CONFIG_GRUB2_EXTRA_MODULES from the Kconfig when building GRUB2.
This causes the specified modules to actually enter the built payload.

Change-Id: I345026af705ba8af77c6c12aba8e1bd4135e519c
Signed-off-by: Benjamin Barenblat <bbaren@google.com>
Reviewed-on: https://review.coreboot.org/15203
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
2016-06-21 18:42:08 +02:00
Alexander Couzens 2c68b1c732 cbfstool: Change CONFIG_FMD_GENPARSER if not set to n
When doing make in util/cbfstool it contaminates the tree because it generates
the fmd_parser.

Change-Id: Ida855d1e57560c76d3fcfcc8e2f7f75bcdfdd5d4
Signed-off-by: Alexander Couzens <lynxis@fe80.eu>
Reviewed-on: https://review.coreboot.org/15221
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>
2016-06-21 17:55:17 +02:00
Werner Zeh 95f6022cb1 flashmap: Use CONFIG_ROM_SIZE as flash size in flashmap
Currently there are two sources for the final size of the
flash image. One is defined as a Kconfig variable
(ROM_SIZE) and the other can be provided in a user defined
flashmap.fmd. This patch will enable the usage of CONFIG_ROM_SIZE
in flashmap.fmd to define the flash size. In this way, the
Kconfig variable is the only source of information for the
flash image size. This way is optional.

Change-Id: Id5298e06d360aaa6d94f2b5a2ffa65e45919853e
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/15219
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-21 17:51:54 +02:00
Julius Werner 119dcee1dd fmaptool: Make base offsets absolute in fmap_config.h
fmaptool generates a header file used to hardcode certain values from
the FMAP in coreboot's binaries, to avoid having to find and parse the
FMAP manually for every access. For the offset of the FMAP itself this
has already been using the absolute offset from the base of the whole
ROM, but for individual CBFS sections it only used the offset from the
immediate parent FMAP region. Since the code using it intentionally has
no knowledge of the whole section tree, this causes problems as soon as
the CBFS is a child section of something not at absolute offset 0 (as is
the case for most x86 Chromebooks).

Change-Id: If0c516083949fe5ac8cdae85e00a4461dcbdf853
Reported-by: Rolf Evers-Fischer <embedded24@evers-fischer.de>
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/15273
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-06-21 17:14:27 +02:00
Freddy Paul 8200761912 google/reef: Add ACPI code for trackpad
This patch enlists ELAN trackpad on I2C4 for reef board.

BUG=None
TEST=Build and boot to OS.
     Ensure ELAN trackpad is working with ELAN trackpad driver enabled
     in kernel.

Change-Id: I788600f16dea9fac0e089cb82ccfc38a960157f9
Signed-off-by: Freddy Paul <freddy.paul@intel.com>
Reviewed-on: https://review.coreboot.org/15213
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-21 17:10:12 +02:00
Freddy Paul 1706cb3ee3 soc/intel/apollolake: make gpo.h ACPI compatible
BUG=None
TEST=Build with <soc/gpio.h> included in mainboard.asl

Change-Id: Id6fdc50d09c014f930fdfd5c2fde0df827ad5181
Signed-off-by: Freddy Paul <freddy.paul@intel.com>
Reviewed-on: https://review.coreboot.org/15272
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
2016-06-21 17:08:31 +02:00
Kyösti Mälkki 15fa992cc8 intel/model_6ex: Prepare for dynamic CONFIG_RAMTOP
Change-Id: I9bfaa53f8d09962d36df1e86a0edcf100bb08403
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/15229
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-21 00:49:12 +02:00
Gabe Black 4c3de9c3ed beaglebone: Update bootblock.c to use new structs/code
New structures and functions have been added to make it easier and
clearer to talk to GPIOs, configure the clock module, and toggle the
LEDs. Use that code in bootblock.c instead of doing those things
manually with hardcoded addresses.

Change-Id: If41db0220de4bc95a6c99945ec402e3026cb4eeb
Signed-off-by: Gabe Black <gabeblack@chromium.org>
Signed-off-by: Alexander Couzens <lynxis@fe80.eu>
Reviewed-on: https://review.coreboot.org/3944
Tested-by: build bot (Jenkins)
Reviewed-by: David Hendricks <dhendrix@chromium.org>
2016-06-21 00:46:42 +02:00
Matt DeVillier 41bcf8adbf mb/google: remove superfluous header includes in bdw chromeboxes
Change-Id: I71443c7547a113bf9b64d48fe5a85c6e2302c8aa
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/15208
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
2016-06-21 00:44:58 +02:00
Kyösti Mälkki 408d392823 intel/car/cache_as_ram_ht.inc: Prepare for dynamic CONFIG_RAMTOP
Change-Id: Idb0f621553e76e771a5d6f2d492675ccd989d947
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/15228
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-21 00:43:20 +02:00
Kyösti Mälkki 07921540dd intel/car/cache_as_ram.inc: Prepare for dynamic CONFIG_RAMTOP
Change-Id: I02881ce465cb3835a6fa7c06b718aa42d0d327ec
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/15227
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
2016-06-21 00:39:47 +02:00
Gerd Hoffmann 633c57d1d1 qemu/x86: car: drop pointless code, move stack out of the way
RAM doesn't need any initialization on qemu, so we can simply use it
right away.  No need to try using the cache as ram in the first place.

We also can place the stack in normal ram right from start and we
don't have to switch it to another place later on.  Place the stack
in real mode memory which isn't used for something else.

Change-Id: Ib7a3f58a846d139f7babea5f43722a30fe0fe962
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
Reviewed-on: https://review.coreboot.org/15214
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2016-06-21 00:35:32 +02:00
Jonathan Neuschäfer 710566093a riscv-spike: Move coreboot to 0x80000000 (2GiB)
This is where the RAM is (now), on RISC-V.

We need to put coreboot.rom in RAM because Spike (at the moment) only
supports loading code into the RAM, not into the boot ROM.

Change-Id: I6c9b7cffe5fa414825491ee4ac0d2dad59a2d75c
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/15149
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-21 00:11:49 +02:00
Jonathan Neuschäfer 2459f67731 util/riscvtools: Add script that turns coreboot.rom into an ELF
This is required because SPIKE doesn't support loading flat files yet.

Change-Id: If745d78712ca8108b5dcc21591201bc2d3f70b86
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/14964
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-21 00:10:14 +02:00
Hannah Williams 057ac4da0e soc/apollolake: Include PCI _OSC method
Change-Id: I2545fc184ebfaa006a75783bf3d55f009066eed3
Signed-off-by: Hannah Williams <hannah.williams@intel.com>
Reviewed-on: https://review.coreboot.org/15110
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-06-20 23:51:29 +02:00
Ryan Salsamendi 5b9a253ae9 Update SeaBIOS URL to https
Change-Id: If1c37bf2bb7df35d5e5ec37cefb9bb92a251f93b
Signed-off-by: Ryan Salsamendi <rsalsamendi@hotmail.com>
Reviewed-on: https://review.coreboot.org/15206
Tested-by: build bot (Jenkins)
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-by: Antonello Dettori <dev@dettori.io>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-06-20 23:50:49 +02:00
Kyösti Mälkki 072d436b3f ACPI S3: Cleanup RSDP reference
Variable name shadows parameter name used on other functions,
and it can be local anyway after function removal.

Change-Id: I3164b15b33d877fef139f48ab2091e60e3124c3b
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/15240
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2016-06-20 22:14:12 +02:00
Hannah Williams f2a50d1231 soc/intel/common: Add _OSC method
Not masking any bits in Operating System Capabilities, which means we
support all the capabilities that OS passed in Arg3

Change-Id: Ib87915e18e305db41b52891ac5430201dda64bb5
Signed-off-by: Hannah Williams <hannah.williams@intel.com>
Reviewed-on: https://review.coreboot.org/15021
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-06-20 22:08:54 +02:00
Patrick Rudolph 55409ebbb6 nb/intel/sandybridge/raminit: Use supported CAS
Instead of programming unsupported CAS use the highest supported
value. Start at DDR3 maximum of CAS 18T.
Increase error message verbosity level.

Useful for overclocking.

Tested on Lenovo T520 and DDR3-1600 DIMM (RMT3170eb86e9w16).
Allows to run a DDR3-1600 DIMM at 933Mhz.

Change-Id: I2e8aadd541f06fa032ad7095c9a2d5e3bb7613f3
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/15217
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
2016-06-20 22:00:40 +02:00
Patrick Rudolph d4c53e3fdd nb/intel/sandybridge/raminit: Do code cleanup
Calculate the value from current DDR frequency.

Tested on Lenovo T520 and DDR3-1600 DIMM (RMT3170eb86e9w16).

Change-Id: I57ffbfeb291fc2fede278d18527993e7432e9bd8
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/15184
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
2016-06-20 21:55:54 +02:00
Patrick Rudolph 4307835d26 arch/x86/smbios: Add DRAM manufacturer
Add Ramaxel DRAM manufacturer id.

Tested on Lenovo T520 and DDR3-1600 DIMM (RMT3170eb86e9w16).
The manufacturer name shows up in dmidecode.

Change-Id: I14cdc82c09f0f990e2ba18083748d11d79e53874
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/15183
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-06-20 21:48:32 +02:00
Patrick Rudolph 577aad6f13 include/device/dram/ddr3: Add additional frequencies
IvyBridge memory controller supports more frequencies than SandyBridge.
Required for future patches.

Change-Id: I0bcb670c20407ec0aec20bae85c4cbe6ccc44b16
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/15182
Tested-by: build bot (Jenkins)
Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2016-06-20 21:46:58 +02:00
Patrick Rudolph b7b1b2884f nb/intel/sandybridge/raminit: Do code cleanup
Simplify calculation of value.

Tested on Lenovo T520 and DDR3-1600 DIMM (RMT3170eb86e9w16).

Change-Id: I3ecd12c431b46a8d2218f33d7eb3e10de3bcd61d
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/15181
Tested-by: build bot (Jenkins)
Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-06-20 21:44:50 +02:00