Hynix H9JCNNNBK3MLYR-N6E will be used for nereid P1. Add it to the parts
list and regenerate the SPDs using spd_gen.
BUG=b:217096008
TEST=None
Signed-off-by: Reka Norman <rekanorman@google.com>
Change-Id: I8775fe0551e0712507d42a778e04745a07270d71
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61904
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Mainboards using Sabrina SoC will be using LP5 memory technology.
Generate the initial set of SPDs for the existing LP5 memory parts.
BUG=b:211510456
TEST=util/spd_tools/bin/spd_gen spd/lp5/memory_parts.json lp5
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: Ibb43f26b36460290341c5ffcad1ef5a2ff1647c8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61543
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reka Norman