The PWM-granularity chicken bit in the Wildcat Point and Lynx Point
PCHs has actually the opposite meaning of the one for Sunrise Point
and later. When the bit is set, we get a divider of 16, when it's
unset 128. Flip the bit!
Change-Id: I1dbde1915d8b269c11643a1636565a560eb07334
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39770
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
_DCS, _DGS and _DSS are required by specification. However,
we never implemented them properly, and no OS driver com-
plained yet. So we stub them out and keep the traditional
behavior in case an OS driver checks for their existence.
The old implementations also only returned static values as
there never was any write to their GNVS variables. The TRAP()
that was called in one place is actually implemented by some
ThinkPad's SMI handler as docking event. However, as the call
precedes these SMI handlers in coreboot history, it's most
likely an accident.
Change-Id: Ib0b9fcdd58df254d3b2290900e3bc206a7abd92d
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39726
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
The format for VPD has changed s.t. the first NIC should
always have a zero concat to the end. drivers/net supports
this with the workaround of setting the idx to 1.
The longer term fix is to adjust all the respective boards
to shift back by one and adjust drivers/net friends to
remove the 'special casing' of idx == 0.
Background:
https://chromeos.google.com/partner/dlm/docs/factory/vpd.html#field-ethernet_macn
BUG=b:152157720
BRANCH=none
TEST=none
Change-Id: I510428c555b92398a5199b346dffb85d38495d74
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39768
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sam McNally <sammc@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
According to the latest Tigerlake Platform FSP Integration Guide, the
minimum amount of stack needed for FSP-M is 256KiB. Change
DCACHE_BSP_STACK_SIZE to reflect that (plus 1KB previously determined
empirically). JSL requires 192KiB.
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: Ic9be6446c4db7f62479deab06ebeba2c7326e681
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39706
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Northbridge IOAPIC was not being initialized which caused its APIC ID to
be set to 0 (the same APIC ID as BSP).
TEST=boot Debian Linux on PC Engines apu2
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: Id06ad4c22a56eb3559e1d584fd0fcac1f95f13e7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39700
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Now that we have it, we might as well pass it around.
Tested on Asus P8Z77-V LX2, still boots fine.
Change-Id: Ia5aa2f932321983f11d2f8869aa624832afe9347
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39721
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Native raminit asserts that the DIMMs haven't been replaced before
reusing the saved training data. However, it does not check if the CPU
is still the same, so it can end up happily reusing data from an Ivy
Bridge CPU onto a Sandy Bridge CPU, which runs the raminit_ivy.c code
path. This can make the CPU run in unsupported configurations, which may
result in an unstable system, or a failure to boot.
To prevent that, ensure that the stored CPUID matches the CPUID of the
installed CPU. If they differ, print a message and do not use the saved
data. As it does not pose a problem for a regular boot, but precludes
resuming from S3, use different loglevels depending on the bootpath.
Tested on Asus P8Z77-V LX2 with an i7-2600 and an i5-3330, works well.
Change-Id: Ib0691f1f849b567579f6afa845c9460e14f8fa27
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39734
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Instead of storing an int with a single bit of information taken from
the CPUID, we might as well store the actual CPUID. And since we are
changing the definition of the saved data, bump the version number.
Tested on Asus P8Z77-V LX2, still boots fine.
Change-Id: I6ac435fb83900a52890f823e7614055061299e23
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39720
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
When changing any of the structures that are cached in non-volatile
storage, it is necessary to bump MRC_CACHE_VERSION so that the old
information is not misinterpreted.
Change-Id: Idefbc38b3a8198b1b5909e775b3c289db689fc0c
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39756
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Header files are supposed to not make allocations from .bss. Builds
fail if said file is included multiple times. To prevent this from
happening, move the definitions to a C file.
Also, rename raminit_patterns to raminit_tables. This is because more
tables that are not patterns will be added here in subsequent changes.
Tested on Asus P8Z77-V LX2, still boots fine.
Change-Id: If8e3a285ecdc4df9e978ae156be915ced6e1750b
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39754
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Make them fit in 96 characters, so that Jenkins does not complain.
With BUILD_TIMELESS=1, the binary of ASUS P8Z77-V LX2 remains identical.
Change-Id: I4a763f6050593e9d4db9211bfeedb442724e1ace
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39719
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The ACPI Spec 2.0 states, that Processor declarations should be made
within the ACPI namespace \_SB and not \_PR anymore. \_PR is deprecated
and is removed here for Intel CPUs only.
Tested on:
* X11SSH (Kabylake)
* CFL Platform
* Asus P8Z77-V LX2 and Windows 10
FWTS does not return FAIL anymore on ACPI tests
Tested-by: Angel Pons <th3fanbus@gmail.com>
Change-Id: Ib101ed718f90f9056d2ecbc31b13b749ed1fc438
Signed-off-by: Christian Walter <christian.walter@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37814
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
According to BKDGs these northbridges should support the K10
compatible temperature sensors.
TEST=boot FreeBSD on PC Engines apu2 and check the thermal zone
temperature using sysctl
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: Icbdf44508085964452d74e084b133f1baa39e1a8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38755
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
According to BKDGs HTC temperature limit field indicates the threshold
where HTC becomes active. HTC active state means that processor is
limiting its power consumption and maximum P-State. Using this threshold
as _CRT is incorrect, since HTC active is designed to prevent
overheating, not causing immediate shutdown.
Change the behavior of temperature limit to act as a passive cooling
threshold. Make the passive cooling threshold a reference value for
critical and hot temperature with 5 degrees step.
TEST=boot FreeBSD on PC Engines apu2 and check the thermal zone
temperature using sysctl
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: Ife64c3aab76f8e125493ecc8183a6e87fb012e3b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39697
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Fixes a blunder in commit 50db9c99be
(nb/intel/sandybridge: Use DIV_ROUND_UP macro to select timings).
Tested on Asus P8Z77-V LX2, still boots fine with an i7-2600.
Change-Id: I73436b9f7df9f3a065469fb89bcd0cc6183bb774
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39736
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
A certain somebody (that would be me) forgot how to count, it seems.
Change-Id: Iac0ac5827ca242c465a2e8be92a823c8fc9b2935
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39741
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
IRQ 0x70 was not declared for device 2e.7, and coreboot whined about it.
Change-Id: If40aa390722cf253169003129b31f20543fde5dd
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39739
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Linux does not handle either value in any special way, though.
Change-Id: I833cb94e65b9ddfb79edbcdd0216c70740aa4a16
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39738
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Add camera ACPI configuration for Ripto/Volteer
BUG=None
BRANCH=None
TEST=Build and boot Ripto or Volteer. Start camera app and able to
capture images.
Signed-off-by: Daniel Kang <daniel.h.kang@intel.com>
Change-Id: I2b47ccd989192273a29f09bf097e12e357929334
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39684
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
This is required for PD notifications on the cros_ec driver.
BUG=b:150649744
TEST=Boot volteer with this patch and verify that PD notifier events are
being generated.
Signed-off-by: Prashant Malani <pmalani@chromium.org>
Change-Id: I2e72320b025a3dfa7412181586cb142a4503eda5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39675
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Use information provided by AGESA to fill the SMBIOS memory tables.
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: Id73de7c2b23c6eb71722f1c78dbf0d246f429c63
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38343
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Camera ACPI had an incorrect board config flag for TGL-UP4.
BUG=None
BRANCH=None
TEST=Build and boot TGLRVP-UP3 or UP4. Start camera app and able to
capture images.
Signed-off-by: Daniel Kang <daniel.h.kang@intel.com>
Change-Id: Ided0e146a9240169d3f1f27a86218ac1a942b899
Signed-off-by: Daniel Kang <daniel.h.kang@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39682
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
It does not make sense to disable an optimization that was not enabled
before, especially if that optimization only applies to Ivy Bridge.
Tested, still boots and can suspend correctly with:
- Asus P8Z77-V LX2 with i5-3330 and Windows 10
- Gigabyte GA-H61MA-D3V with i5-2400 and Arch Linux
Change-Id: I9f3eb545585824bbdf51e33f0592e7daa1c425af
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39623
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
This patch replaces hard-coded PCI IDs with macros from pci_ids.h and
adds the related IDs to it.
The resulting binary doesn't differ from the one without this patch.
Used documents:
- Intel 322170
Change-Id: I3326f142d483f5008fb2ac878f30c1a3a72f500f
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37116
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Michael Niewöhner
Use the version from native raminit, as it takes the reference clock
into account.
Change-Id: I00e979bec236167d22561e3eb44b30b4a34ad663
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39622
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Enable GPIO functionality in verstage so platforms can read a
PCH GPIO in verstage to determine recovery mode.
BUG=b:151102807
TEST=make build successful
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Change-Id: I4e3b9da307dcf59ab251d8a6a5e09c2a3cfc59fe
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39501
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Check that there are actually USB-PD ports for which to
add data to SSDT, before actually generating SSDT data.
This prevents an empty scope from being generated on
devices without any USB-PD ports, which was breaking
parsing/decompilation on some older platforms (eg,
Braswell).
Test: build/boot google/edgar, verify SSDT table able to
be parsed via iasl after dumping.
Change-Id: Ia213e5815e9160e9b36b2501eeccb6385abef47e
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39665
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This register needs to be written to once to lock it down. Do so.
Change-Id: I04bd496d064940b51cb9aa1ded6f5b8853ea7334
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39624
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Nico Huber