Commit Graph

39730 Commits

Author SHA1 Message Date
Angel Pons 739a6ad1ac mb/google/auron: Use Haswell CPU code
The VR config and S0ix options are now specified for the CPU chip.

Change-Id: I75e405d41b4a0605e786fe761c92535e62d0cfce
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46945
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-24 12:03:08 +00:00
Angel Pons d0b7a534ce mb/google/jecht: Use Haswell CPU code
Change-Id: I6c106b152bb2824e000232d23c2991898b2c4475
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46946
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-24 12:02:43 +00:00
Angel Pons b7fe448575 mb/intel/wtm2: Use Haswell CPU code
Change-Id: I478576afa3b390cf5480298aafe6e049b5e90bff
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46947
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-24 12:02:34 +00:00
Angel Pons ba78fce868 mb/purism/librem_bdw: Use Haswell CPU code
Change-Id: I736bff90305952d279a10dfe90a2ee3a533220b5
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46948
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-24 12:02:25 +00:00
Angel Pons a3288b38e1 soc/intel/broadwell: Allow to use Haswell CPU code instead
This allows individual boards to be adapted to use Haswell CPU code.
Also rename the CPU_SPECIFIC_OPTIONS symbol to avoid any collisions.

Change-Id: I65e878dacf0a0d53fd8d4defce6684f4ceb92588
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46944
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-24 12:02:15 +00:00
Angel Pons 417a6da449 soc/intel/broadwell: Select INTEL_LYNXPOINT_LP
This allows the correct Haswell and Lynxpoint code to be used.

Change-Id: Icbfc5bb11b1ea755a143fa340a3971376f4e5e91
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46958
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-24 12:01:31 +00:00
Angel Pons f542b7bcef cpu/intel/haswell: Add Broadwell CPUIDs and microcode
Broadwell can now use the Haswell CPU driver.

Change-Id: I36138cab72b1e3ad0ff7f6434996f5ce00de9d0d
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46942
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-24 12:01:24 +00:00
Angel Pons 1c7ba62eb7 cpu/intel/haswell: Set C9/C10 vccmin
Backport commit ab7586fa26 (broadwell: Set C9/C10 vccmin) to Haswell.

Change-Id: I9cddc7dd45e96c6f99327ee2583917bf8bedfbdd
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46922
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-24 12:01:09 +00:00
Angel Pons c86b119495 cpu/intel/haswell: Add fast ramp voltage for Broadwell
Backport commit 55228ba4b4 (broadwell: Changes from 2.2.0 ref code) to
Haswell, to eventually migrate Broadwell to use the same Haswell code.

Change-Id: I03d9ff16bcaab9091bd723ce933aa3f2d71e29b9
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46921
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-24 12:00:59 +00:00
Raul E Rangel 8b043c058c lib/edid_fill_fb: Relax bits_per_pixel constraint
The Picasso VBIOS is not setting the reserved_mask_size correctly. This
change relaxes the constraint to allow bpp_mask <= bits_per_pixel. This
is how the code previously used to work before CB:39002.

BUG=b:177094598, b:177422379
TEST=boot zork and see depthcharge working

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I2e67532fa949fbd673269d8d7f1c0d8af6124ac9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49404
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-01-24 11:18:23 +00:00
Kyösti Mälkki d4b58259c4 soc/intel/baytrail,broadwell: Use bootstate for save_wake_source()
Change-Id: I01be1b9dfefcfcf037de4153e9540c7258dc160f
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49818
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-23 20:32:01 +00:00
Kyösti Mälkki 2787237dd5 ACPI: Add helpers for CBMEM_ID_POWER_STATE
Create uniform logging for the (unlikely) case of a CBMEM
entry disappearing.

Change-Id: I7c5414a03d869423c8ae5192a990fde5f9582f2d
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49817
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-01-23 20:31:09 +00:00
Kyösti Mälkki 10f7f997ad soc/amd: Rename chipset_state to chipset_power_state
To implement some common helpers for CBMEM_ID_POWER_STATE
allocation use the same struct name as soc/intel.

Change-Id: I5d2c06a2a7b4602374562197c99b0ad7bcf50afb
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49835
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-01-23 20:21:14 +00:00
Kyösti Mälkki ac0dc4a840 ACPI S3: Replace stashed acpi_slp_typ value
We currently have a mixture of calls used to determine
global ACPI S3 state. Reduce the boilerplate, ultimately
acpi_wakeup_is_s3() should be the only to keep.

Change-Id: Iff950d2bcf7eacbbdd40865abf62c35a2e8c3c69
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47694
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-23 20:19:47 +00:00
Kyösti Mälkki 540902ca47 intel/baytrail,braswell,broadwell: Add const qualifier for power_state
Change-Id: I37781c1423b49130ffd0d5f9fbdd28a36c9c6179
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49821
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-01-23 20:18:29 +00:00
Kyösti Mälkki 6b43055b7a ELOG: Add const qualifier for chipset_power_state
It is never allowed for ELOG to modify the state.

Change-Id: Ie24df3969a3744f27b23997471666e2490e24b84
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49820
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-01-23 20:18:11 +00:00
Raul E Rangel 0052d05101 soc/amd/picasso/pcie_gpp: Remove duplication in pirq_data declaration
There is no reason to duplicate the table.

BUG=b:170595019
BRANCH=zork
TEST=boot zork with pci=nomsi and verify /proc/interrupts didn't change

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Ief714266cdb1b4f89afd0d9e50238200b87687ef
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49367
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-01-23 20:14:42 +00:00
Raul E Rangel b5e27a81cc soc/amd/picasso/pci_gpp: Replace the swizzle string with a u8 array
I think it makes the code a bit cleaner.

BUG=b:170595019
BRANCH=zork
TEST=boot zork with pci=nomsi and verify /proc/interrupts didn't change

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Ib5e8e5b690d9612e8ae257f5d15c25122e1c91e6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49842
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-01-23 20:14:34 +00:00
Raul E Rangel 91839eef5c soc/amd/picasso/pcie_gpp: Add clarifying comment
Each bridge can only have one device.

BUG=b:170595019
BRANCH=zork
TEST=none

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I7e476221dfcabc841cc1ed4bc4b1175c0652dcfe
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49841
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-01-23 20:14:28 +00:00
Zheng Bao 76e72a0dd5 mb/google/guybrush: Set FWM position to an upper address
Setting other places causes build error.

BUG=b:178241112
TEST=Build

Change-Id: I85d5d44c458feed38d69f21f899d6b4380963ec7
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49825
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-01-23 20:10:20 +00:00
Raul E Rangel 7c0e49b24a soc/amd/picasso/acpi: Remove dummy AOAC parent device
The dummy AOAC parent device was nice because it grouped all the AOAC
devices. Unfortunately windows doesn't like this dummy device and causes
"Not Found" errors. This change moves the AOAC devices to the actual
devices that use them.

BUG=b:175146875
TEST=Boot linux and make sure power resources are enabled/disabled.

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Idd4a94baa4358ee4f15c461a5bb54ca925023a13
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49814
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-01-23 17:31:12 +00:00
Tim Crawford 0698f0f354 soc/intel/cometlake: Add ucode for CML-H
Add microcode from 3rdparty repo for:
- 06-a5-02 (CPUID signature: 0xa0652)

Change-Id: I95419f44a1e804ce31338fe6d863f156c655321b
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47915
Reviewed-by: Jeremy Soller <jeremy@system76.com>
Reviewed-by:  Felix Singer <felixsinger@posteo.net>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-23 17:00:31 +00:00
Tim Crawford 8818ddab82 3rdparty/intel-microcode: Update submodule to 20201118 release
Update submodule pointer to include microcode for CML-H and others.

Change-Id: Ide211b0b163f824a3cfa6500a73aea1e2176c652
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47914
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by:  Felix Singer <felixsinger@posteo.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-23 17:00:15 +00:00
Angel Pons 3ece16410f mb/google/auron: Drop `variant_romstage_entry`
Replace it with `mainboard_post_raminit`.

Change-Id: I94636c775cee6c14317ecff36972e2d267d28c91
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49774
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-01-23 13:35:47 +00:00
Angel Pons 292a764141 mb/google/auron: Factor out SPD indexing
The code to read the SPD file and index it is not variant-specific.

Change-Id: Iaee0a77934a45c65bf32dd0dba23cec654abc0b9
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49773
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-01-23 11:25:59 +00:00
Angel Pons e23b0abe30 mb/google/auron: Factor out `mainboard_print_spd_info`
It is identical for all variants that have it.

Change-Id: Iec3a5f036d9b760d1075059f2db1480b1c76273e
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49772
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-01-23 11:24:30 +00:00
Angel Pons 465b2a8f00 mb/google/auron: Merge two print statements
They are part of the same line, so merge them.

Change-Id: I969ce91f7a5f16a85750c140eaa444d7923b2014
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49771
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-01-23 11:24:05 +00:00
Angel Pons af4e8e82c6 mb/google/auron: Drop `spd.h` from variants
Factor out common DRAM SPD definitions and relocate SPD GPIO macros.
Also factor out common function definition. Drop now-empty headers.

Change-Id: Id05ba6c9cea27fbad5ee831f033d0de43717847e
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49770
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-01-23 11:23:58 +00:00
Michael Niewöhner 58a3f765e9 mb/intel/coffeelake_rvp: do UART pad configuration at board-level
UART pad configuration should not be done in common code, because that
may cause short circuits, when the user sets a wrong UART index. Thus,
add the corresponding pads to the early UART gpio table for the board as
a first step. Common UART pad config code then gets dropped in CB:48829.

Also switch to `bootblock_mainboard_early_init` to configure the pads in
early bootblock before console initialization, to make the console work
as early as possible. The board does not do any other gpio configuration
in bootblock, so this should not influence behaviour in a negative way
(e.g. breaking overrides).

Change-Id: Ib827e9b2919dbd0e16f30b8dfde46348365d9622
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49438
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-01-23 09:23:51 +00:00
Michael Niewöhner d509ee55b6 soc/intel/apl: drop LPC pad configuration code
Drop LPC pad configuration code since all boards now do pad
configuration on their own. The comment about LPC_CLKRUNB when using
eSPI is moved to `Documentation/getting_started/gpio.md`.

Change-Id: I710d6aee8c3b2c8282cd321cd0688b9b26abea07
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49410
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-23 09:23:23 +00:00
Subrata Banik d5ab1267e5 drivers/intel/fsp2_0: Add meaningful ERROR message
Add the "ERROR:" tag so that it ease debug effect.

TEST=Test tools like "suspend_stress_test" (specific to Chrome OS) can
identify the obvious coreboot ERROR prior running S3 resume test.

Change-Id: I64717ce0412d43697f42ea2122b932037d28dd48
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49798
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-23 04:27:33 +00:00
Karthikeyan Ramasubramanian dd4741c7bd vendorcode/google/chromeos: Build CSE Board Reset in Romstage
CSE Firmware Sync is being performed in romstage currently. But the CSE
board reset is not included as part of romstage. This causes the CSE
firmware sync to use global reset instead of EC assisted AP reset with
the old Cr50 Firmware version. Include the board specific CSE reset in
romstage.

BUG=b:171731175,b:177795247
BRANCH=dedede,volteer,puff
TEST=Ensured that the Drawlat boots to OS with both old(0.0.22) and
new(0.6.7) Cr50 FW versions.

Change-Id: I5e362271ffb68ffd5884279acd1ab0a462195a8a
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49850
Reviewed-by: Evan Green <evgreen@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-22 22:53:07 +00:00
Martin Roth d736b1a607 util/docker: Replace all variables in Dockerfile
When updating the variables in the dockerfile, if there were two or more
variables on a line, only the first would be updated.  This fixes that
issue.

Change-Id: I011ccb299c7c8527b79d234075cab18be998ab43
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47339
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-01-22 21:27:44 +00:00
Felix Held 0728c46925 soc/amd/cezanne: add pci_devs.h
Change-Id: I9e3ee4c98a85068dc87ef96aaf65a09c6df1572d
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49781
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-01-22 19:30:13 +00:00
Zheng Bao 0ada720d03 mb/amd/majolica: Add PSP support for board majolica
Change-Id: Ia2470a7297c7003c7975c7d9b977f2f97174efea
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48529
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-22 15:45:39 +00:00
Zheng Bao aba6715fe2 mb/google/guybrush: Set the ROMSIZE as 16M
Change-Id: Iec8b40bd89c25cd2193aff8af45d0a09b07ad6a3
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49797
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-22 15:09:01 +00:00
John Zhao eec3e3b3d9 ec/google/chromeec: Provide EC access for Retimer firmware update
Kernel needs to access EC RFWU entry in order to retrieve from EC about
port and mux info and set EC operations like modes change. This change
provides EC RFWU path and update for Retimer driver usage.

BUG=b:162528867
TEST=Booted to kernel and verified EC RFWU path from ACPI SSDT table.

Signed-off-by: John Zhao <john.zhao@intel.com>
Change-Id: I3817d93cfdeedf15825dab6c537b151fd063338b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49257
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-22 14:28:20 +00:00
John Zhao 408e5ab6c9 ec/google/chromeec: Add RFWU into EC RAM for Retimer firmware update
The RFWU byte is defined as Bits[3:0] for port number and Bits[7:4] for
operations. The supported operations are:
RETIMER_FW_UPDATE_PORT_INFO	0
RETIMER_FW_UPDATE_PD_SUSPEND	1
RETIMER_FW_UPDATE_PD_RESUME	2
RETIMER_FW_UPDATE_GET_MUX	3
RETIMER_FW_UPDATE_SET_USB	4
RETIMER_FW_UPDATE_SET_SAFE	5
RETIMER_FW_UPDATE_SET_TBT	6
RETIMER_FW_UPDATE_DISCONNECT	7

BUG=b:162528867
TEST=Booted to kernel and verified RFWU entry from ACPI DSDT ERAM field.

Signed-off-by: John Zhao <john.zhao@intel.com>
Change-Id: I1ba04c6357b6fd0cc33ffce33e7e430539bace79
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49051
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-22 14:28:14 +00:00
Brandon Breitenstein 297d27b8bb drivers/intel/usb4: Enable retimer FW upgrade mux interaction
In order to update the BB retimers for usb4/tbt they need to be turned
on and into TBT mode. Expand the current DSM to allow for the use of an
EC RAM byte RFWU to get the current state of each port and whether or
not it has a retimer. It also allows Kernel to issue state transitions
for the retimer to be put into TBT mode for firmware update.

BUG=b:162528867
TEST=Along with work in progress kernel and EC patches, the Retimer
firmware update is verified under device attached and no device attached
scenarios.

Change-Id: I768cfb56790049c231173b0ea0f8e08fe6b64b93
Signed-off-by: Brandon Breitenstein <brandon.breitenstein@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48630
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-01-22 14:28:08 +00:00
Frans Hendriks 3a7db27f45 sconfig: Handle smbios_slot_desc in overridetree
SMBIOS slot information in overrridetree is not overriden
if device already exist in devicetree.

Add support to handle this information from override.

BUG= N/A
TEST= Verify generated static.c on Intel Coffee Lake CRB

Change-Id: I532436aee1d71b79171463124f7b205c145d5b05
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49738
Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-22 14:27:56 +00:00
Patrick Rudolph 1b5b41a790 mb/prodrive/hermes: Fix 30 second boot delay
The PMC doesn't response any more due to invalid CNVi GPIO
configuration. This caused a 30 second boot delay in FSP-S.

Use the same values as FSP-S does. Always disable external I2S BT
audio and use NF3 for pad GPP_D5 and GPP_D6.

Tested on Prodrive hermes:
No boot delay can be observed any more.

Change-Id: I6f4a954786ec21512b0dce908d333952e96de048
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49678
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-22 14:27:45 +00:00
Tony Huang 8ab253c9a9 mb/google/octopus: Garfour override VBT selection
Disable DRRS in VBT to solve panel flick issue

SKU ID
49/51 will use vbt_garfour.bin
50/52 will use vbt_garfour_hdmi.bin

BUG=b:177783330
BRANCH=octopus
TEST=emerge-octopus coreboot chromeos-bootimage
     check /run/debug/i915_drrs_status shows DRRS supported NO.

Cq-Depend: chrome-internal:3534569
Change-Id: I5ebb66ec043a6b409dd5abbc31da417f50dbad5c
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49635
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-22 14:27:23 +00:00
Seunghwan Kim 9f5c365e6d mb/google/nightfury: Update RAM IDs usage
Add support LP_16G_2133 SPD for nightfury.

BUG=None
BRANCH=firmware-hatch-12672.B
TEST=emerge-hatch coreboot

Change-Id: I3709431d8ecb600e25909f456eb0c95db3a3cde2
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49735
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-01-22 14:27:15 +00:00
Furquan Shaikh 197c486997 types.h: Add a helper macro BITS_PER_BYTE
This change adds a helper macro `BITS_PER_BYTE` so that it doesn't
have to be defined in multiple places.

Change-Id: Idc344047a5660791eaeb1ce8012910c11f6010ba
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49736
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-01-22 14:26:58 +00:00
Varshit Pandya b5df56f6f2 soc/intel/alderlake: Adding Kconfig for ADL_M PCH
1. Add SOC_INTEL_ALDERLAKE_PCH_M option in Kconfig
2. Select number of I/O based on PCH

Signed-off-by: Varshit Pandya <varshit.b.pandya@intel.com>
Change-Id: I38783595e4b85abf5b3bec234ba01667bd9ba754
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49630
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-22 14:26:44 +00:00
Varshit Pandya f4d98fdd20 soc/intel/commmon: Include Alder Lake device IDs
Add Alder Lake M specific CPU, System AGent, PCH (Alder Point aka
ADP),
IGD device IDs.

Document Number: 619501, 626817

Signed-off-by: Varshit Pandya <varshit.b.pandya@intel.com>
Change-Id: Ib13fe229f9e65eae8967aa20e28e29ac5c319265
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49629
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-22 14:26:38 +00:00
Wisley Chen f2d38baa98 mb/google/volteer/var/elemi: Update dptf parameters
Update DPTF setting from thermal team.

BUG=b:177635236
BRANCH=volteer
TEST=emerge-volteer coreboot chromeos-bootimage, and verified by thermal team.

Change-Id: I87256b5c210ef12c09ef6dd948d80f406ae0500b
Signed-off-by: Wisley Chen <wisley.chen@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49682
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2021-01-22 14:26:19 +00:00
Hsin-Hsiung Wang d194081ba6 soc/mediatek/mt8192: pmic: Set efuses manually
Some efuse settings would not be applied automatically, so we need
set the settings manually. The low power consumption would not be
optimal without correct efuse settings.

BUG=b:172636735
BRANCH=none
TEST=see 'pmic_efuse_setting: Set efuses in 11 msecs'

Signed-off-by: Hsin-Hsiung Wang <hsin-hsiung.wang@mediatek.com>
Change-Id: Ideb862c3cb0f1fee183804aed74fcf141bf1f5df
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49006
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-01-22 14:26:08 +00:00
Nick Chen d6375cf556 mb/google/volteer/variants/eldrid: Configure USB2 port for Type-C
1. USB2 ports 3 and 8 assigned to Type-C connector
2. USB2 port 3 keep USB2_PORT_SHORT setting and add .type_c flag

BUG=b:177481076
TEST=tested on eldrid

Signed-off-by: Nick Chen <nick_xr_chen@wistron.corp-partner.google.com>
Change-Id: I42a39318a151bdf1f5aeb84bb1992be128cb4a4d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49452
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-01-22 14:25:58 +00:00
Yu-Ping Wu 37765930ec soc/mediatek/mt8183: Fix pq module size config
For pq module size registers such as DISP_AAL_SIZE, the high bits
should be HSIZE, while low bits should be VSIZE. Fix the incorrect
settings for these registers where width and height are reversed.

According to MediaTek, there is no practical impact on mt8183 devices,
but it's still nice to get this fixed to avoid future confusion.

BUG=b:171167210
TEST=none
BRANCH=kukui

Change-Id: I4b6aedf9a3ca133fcbe9cb88b99a13d228233e24
Signed-off-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46626
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-22 14:25:46 +00:00