Commit Graph

15 Commits

Author SHA1 Message Date
Kyösti Mälkki bf62b2ddb0 AMD fam10: Drop PCI_BUS_SEGN_BITS
All boards in tree use 0.  Looks like this is all work that was
never completed and tested.

We also have static setting sysconf.segbit=0 which would conflict
with PCI_BUS_SEGN_BITS>0.

Having PCI_BUS_SEGN_BITS>0 would also require PCI MMCONF support
to cover over 255 buses.

Change-Id: I060efc44d1560541473b01690c2e8192863c1eb5
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/8554
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-03-09 19:33:08 +01:00
Kyösti Mälkki 754fac4346 PCI subsystem: Remove AGP bridge type
There is no auto-detection for AGP type and we have no hardware that
selects this. Furthermore, we treat AGP bridges just like PCI bridges,
there is no optimisation for higher bandwidth.

Change-Id: I4fe87c83411643cb9b8d3216f2af07bf098174d3
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/8367
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-02-10 09:38:32 +01:00
Martin Roth 98b698c94f src/device: Doxygen fixes
- Add missing parameters
- add missing @param commands

Change-Id: I029b5dafde94bd250800b06c0e9bd2118f10ef48
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: http://review.coreboot.org/8173
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2015-01-12 21:29:38 +01:00
Martin Roth 32bc6b6b84 doxygen fixes: fix parameter names to match the functions
The doxygen parameter names in the comments no longer matched the
functions they were attached to.  Doxygen complains about extra
parameter comments and uncommented parameters in the functions.

Change-Id: I21b8a951f8d8d04b07c3779000eeaf1e69fed463
Signed-off-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-on: http://review.coreboot.org/8101
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-01-06 06:32:37 +01:00
Edward O'Callaghan 6c99250c3f device/pci_device.c: Sanitize headers
Change-Id: I6254f4ab767952cc8ff31bb462c7037b027442ba
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/6079
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-06-25 11:32:24 +02:00
Kyösti Mälkki 58ceb00ea7 PCI VGA ROM: Use acpi_is_wakeup_s3()
Change-Id: I6f9c992f1a68025ed18de57c5856b3bf9a673bfb
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/6075
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-06-21 08:04:55 +02:00
Mike Loptien 0f5cf5e45b PCI IRQs: Swizzle PCI IRQs for PCI bridges
The PCI Specification states that devices that implement
a bridge and a secondary bus must swizzle (rotate) the
interrupt pins according to the table below:
	Child Dev #     Child PIN       Parent PIN
	0,4,8,12...     A/B/C/D         A/B/C/D
	1,5,9,13...     A/B/C/D         B/C/D/A
	2,6,10,14..     A/B/C/D         C/D/A/B
	3,7,11,15..     A/B/C/D         D/A/B/C

Which is also described by this equation:
	PIN_parent = (Pin_child + Dev_child) % 4

When a device is found and its bus number is greater than 0,
it is on a bridge and needs to be swizzled.  Following the
string of parents up to the root bus and swizzling as we go
gives us the desired swizzling result.  When BIOS_SPEW is
defined, it will print out each step of the swizzling process.

Change-Id: Icafeadd01983282c86e25f560c831c9482c74e68
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: http://review.coreboot.org/5734
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-by: Mike Loptien <mike.loptien@se-eng.com>
2014-05-29 23:24:28 +02:00
Kyösti Mälkki 9ab1c106c3 device: Conditionally bypass oprom execution
Builds with CHROMEOS can bypass VGA oprom when boot is not in
developer or recovery modes. Have the same functionality available
without CHROMEOS but with BOOTMODE_STRAPS.

Change-Id: I97644364305dc05aad78a744599476ccc58db163
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5595
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@google.com>
2014-05-01 15:39:52 +02:00
Kyösti Mälkki ab56b3b11c ChromeOS: Remove oprom_is_loaded
A global flag oprom_is_loaded was used to indicate to
U-boot that VGA option ROM was loaded and run, or that
native VGA init was completed on GMA device.

Implement this feature without dependency to CHROMEOS option
and replace use of global variable oprom_is_loaded with call
to gfx_get_init_done().

Change-Id: I7e1afd752f18e5346dabdee62e4f7ea08ada5faf
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/4309
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-05-01 15:39:26 +02:00
Kyösti Mälkki 580e5642a8 device: provide option to always load PCI option roms
Certain kernel drivers require the presence of option rom
contents because the board's static configuration information
is located within the blob. Therefore, allow a chipset/board to
instruct the pci device handling code to always load but not
necessarily run the option rom.

BUG=chrome-os-partner:25885
BRANCH=baytrail
TEST=Both enabling and not enabling this option shows expected behavior.

Change-Id: Ib0f65ffaf1a861b543573a062c291f4ba491ffe0
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/188720
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5594
Reviewed-by: Aaron Durbin <adurbin@google.com>
Tested-by: build bot (Jenkins)
2014-05-01 15:38:11 +02:00
Vladimir Serbinenko b32816e9a5 Remove PCI_ROM_RUN option
The main purpose of option rom is to supply int* handlers.
But supplying those is outside of coreboot scope and if someone needs those
they should run SeaBIOS anyway which runs the option roms wonderfully.

Running VGA oprom is kept because they're needed to init graphics.

This patch still keeps the options to include the option roms to make them
available to SeaBIOS.

Change-Id: I646334cf88094d3bf8f527779a68a07e0b4b93ec
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/4545
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-by: Kevin O'Connor <kevin@koconnor.net>
2013-12-24 14:40:49 +01:00
Duncan Laurie 7e1c83e31b Add Kconfig options to override Subsystem Vendor and Device ID
These can typically be set in the devicetree but we need a way to
override those values with a Kconfig setting so as not to expose
the Vendor ID before the product has launched.

Change-Id: Ib382e6d9359d24b128c693a657ffde52604efad3
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/65310
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/4455
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21 12:02:40 +01:00
Kyösti Mälkki c73acdb69e Add test to match struct device with pci_devfn_t
Add a function to test if pci_devfn_t matches with a device
instance of struct device, by comparing bus:dev.fn.

Change-Id: Ic6c3148ac62c7183246d83302ee504b17064c794
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/3474
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
2013-08-24 07:38:23 +02:00
Aaron Durbin ce872cb9af pci: don't load vga option rom before S3 check
The pci device code was probing and loading the option rom before
it did the S3 resume check for VGA option roms. Instead move this
check before probing and loading so that we don't unnecessarily
do work.

Change-Id: If2e62d0c0e4b34b4f1bcd56ebcb9d3f54c6d0d24
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/2979
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Tested-by: build bot (Jenkins)
2013-04-01 20:55:56 +02:00
Stefan Reinauer 8d7115560d Rename devices -> device
to match src/include/device

Change-Id: I5d0e5b4361c34881a3b81347aac48738cb5b9af0
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/1960
Tested-by: build bot (Jenkins)
Reviewed-by: David Hendricks <dhendrix@chromium.org>
2012-11-30 23:59:58 +01:00
Renamed from src/devices/pci_device.c (Browse further)