This patch changes the way coreboot builds ARM TF to pass the new
COREBOOT flag introduced with the following pull request:
https://github.com/ARM-software/arm-trusted-firmware/pull/1193
Since the new coreboot support code supports the CBMEM console, we need
to always enable LOG_LEVEL INFO. Supporting platforms will parse the
coreboot table to conditionally enable the serial console only if it was
enabled in coreboot as well.
Also remove explicit cache flushes of some BL31 parameters. Turns out we
never really needed these because we already flush the whole cache when
disabling the MMU, and we were already not doing it for most parameters.
Change-Id: I3c52a536dc6067da1378b3f15c4a4d6cf0be7ce7
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/23558
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
According to SMBIOS Reference Specification (1)
section 7.18.5 Memory Device — Extended Size
When the size cannot be represented in the size field, it must be set to
0x7fff and the real size stored in the extended_size field.
1: https://www.dmtf.org/sites/default/files/standards/documents/DSP0134_3.1.1.pdf
Change-Id: Idc559454c16ccd685aaaed0d60f1af69b634ea2e
Signed-off-by: Julien Viard de Galbert <jviarddegalbert@online.net>
Reviewed-on: https://review.coreboot.org/23396
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Some x86 platforms don't have a TSC that is invariant w.r.t.
rate to get accurate timestamps. As such a different timestamp
is required. Therefore, allow one to specify non-TSC timestamp
source and not compile in the default x86 TSC code.
BUG=b:72378235,b:72170796
Change-Id: I737fcbba60665b3bc2b5864269536fda78b44d90
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/23423
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
The PNOT method never notifies the CPU to update it's _CST methods due
to reliance on inexisting variable (PDCx).
Add a method in the speedstep ssdt generator to notify all available
CPU nodes and hook this up in this file.
The cpu.asl file is moved to cpu/intel/speedstep/acpi since it now
relies on code generated in the speedstep ssdt generator. CPUs not
using the speedstep code never included this PNOT method so this is
a logical place for this code to be.
Change-Id: Ie2ba5e07b401d6f7c80c31f2bfcd9ef3ac0c1ad1
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/23144
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
All boards and chips that are still using LATE_CBMEM_INIT are being
removed as previously discussed.
If these boards and chips are updated to not use LATE_CBMEM_INIT, they
can be restored to the active codebase from the 4.7 branch.
chips:
cpu/intel/socket_mFCBGA479
northbridge/intel/i82830
Mainboards:
mainboard/rca/rm4100
mainboard/thomson/ip1000
Change-Id: I9574179516c30bb0d6a29741254293c2cc6f12e9
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: https://review.coreboot.org/22032
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
coreboot only maintains a single trap entry, because it only runs in
machine mode.
Change-Id: I7324d9c8897d5c4e9d4784e7bc2a055890eab698
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/22595
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
The code dealing with the old config string isn't needed anymore,
because the config string has been deprecated in favor of
OpenFirmware-derived devicetrees.
Change-Id: I71398fb4861dbaf7eefc6e6f222bb7159798fafa
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/22594
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
This Supervisor Binary Interface, which is based on a page of code
that's provided to operating systems by the M-mode software, has been
superseded by a different (currently not really documented) SBI, which
is based on directly executing ECALLs instructions. Thus some of our
code becomes obsolete. Just rip it out until we implement the new SBI.
Change-Id: Iec9c20b750f39a2b8f1553e25865bbf150605a6d
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/22593
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
There is currently no case where a struct cpu_device_id instance needs
to be modified. Thus, declare all instances as const.
Change-Id: I5ec7460b56d75d255b3451d76a46df76a51d6365
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/22526
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
The commit 93bbd41e (soc/intel: Enable ACPI DBG2 table generation)
causes a crash on the mainboard mc_apl1. On this mainboard all internal
SOC UARTs in the devicetree are switched off. As a result, no resources
are allocated to the UARTs. The function find_resource() expects an
existing resource. Otherwise, the CPU will stop. It should therefore not
only be queried whether a device is present, but also whether it is
enabled.
Change-Id: I56ce44ae0cf77916fcb640f79fb8944fe33177cd
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/22552
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
This is the lazy solution, as explained in the comment, but it works for
now.
Change-Id: I46e18b6d633280d6409e42462500fbe7c6823b4d
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/21689
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Accessing the config string doesn't work anymore on current versions of
spike. Thus return dummy pointers until we have a better solution.
Change-Id: I684fc51dc0916f2235e57e36b913d363e1cb02b1
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/21687
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Our toolchain can compile mret now, and once the encoding changes, we'll
have to adjust the code anyway.
Change-Id: Ic37a849f65195006fa15d74f651a8aa9a9da5b5c
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/21762
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
This fixes a case of mstatus corruption, where GCC generated code that
used the same register for the mprv bit and the result.
GCC inline assembly register modifiers are documented here:
https://gcc.gnu.org/onlinedocs/gcc/Modifiers.html
Change-Id: I2c563d171892c2e22ac96b34663aa3965553ceb3
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/21688
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Emits a list of CPU cores, e.g.
Name (PPKG, Package (2) { \_PR.CP00, \_PR.CP01 })
Tested on Lenovo Thinkpad T500.
Change-Id: I10e9ebad84343d1fb282b3fbb28f5f014f664f14
Signed-off-by: Nico Huber <nico.h@gmx.de>
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/21324
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The Clang Static Analyzer warns about an unused assignment, when
building the image for the Lenovo X60.
```
src/arch/x86/gdt.c:39:6: warning: Value stored to 'num_gdt_bytes' \
during its initialization is never read
u16 num_gdt_bytes = (uintptr_t)&gdt_end - (uintptr_t)&gdt;
^~~~~~~~~~~~~ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
```
If `CONFIG_RELOCATABLE_RAMSTAGE` is selected, the function returns
before the assignment is used. So, move the assignment below the if
statement.
Change-Id: Ibcb8bce743d8cb3625647804816fb97f937dc429
Found-by: clang version 4.0.1-6 (tags/RELEASE_401/final), Debian Sid/unstable
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://review.coreboot.org/21957
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Martin Roth <martinroth@google.com>
In commit c06a3f72 (arch/x86: initialize EBDA in S3 and S0/S5 path),
BDA and EBDA are wiped in the resume path. It results in coreboot
forwarding table address being wiped out since it is stored in the
BDA. This issue was resolved for platforms using EARLY_EBDA_INIT in
commit f46a9a0d (arch/x86: restore forwarding table on resume for
EARLY_EBDA_INIT). However platforms that do not use EARLY_EBDA_INIT
still run into the same issue and hence cbmem does not work on
resume. This change fixes the issue by using the stash/restore of
forwarding table address for all platforms using BDA.
BUG=b:68412690
TEST=Verified that cbmem works on S3 resume for coral.
Change-Id: I42ae2ccb0b4ce8e989b1032d82b9bb34d0d84db0
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/22207
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
In commit c06a3f72 (arch/x86: initialize EBDA in S3 and S0/S5 path)
the BDA and EBDA are wiped in the resume path. However, the coreboot
table forwarding entry wasn't taken into account so that was wiped
which resulted in cbmem not working on the resume path. Fix this
by stashing the forwarding table in cbmem and restoring it on
the resume path.
Change-Id: I142503535a78635fbb1c698fc7d032c1a2921813
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/22078
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
It's more consistent to re-initialize EBDA in all boot paths.
That way, the data living in EBDA is cleared prior to be
accessed (assuming it's after setup_ebda()).
Change-Id: I05ff84f869f7b6a463e52b4cb954acc5566475cd
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/21997
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
In current versions of spike, the config string is not available
anymore, because RISC-V is moving toward OpenFirmware-derived device
trees (either in FDT or text format). Using query_config_string leads to
a crash in these versions of spike.
With this commit and If0bea4bf52d ("riscv: Update register address"),
coreboot reaches the romstage again, on spike.
Change-Id: Ib1e6565145f0b2252deb1f4658221a4f816e2af4
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/21657
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
This is easier to read than the raw shift amount that's extracted from
load/store instructions.
Change-Id: Ia16ab9fbaf55345b654ea65e65267ed900eb29e1
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/21654
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
I triggered a bug, when I try to debug riscv code by spike.
This bug is caused by an instruction exception[csrwi 0x320,7].
This is operate for mcounteren. This address is error. 0x306
is right. scounteren is not need to be set, because S-mode
code controls it.
Change-Id: If0bea4bf52d8ad2fb2598724d6feb59dc1b3084a
Signed-off-by: wxjstz<wxjstz@126.com>
Reviewed-on: https://review.coreboot.org/20043
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
This patch provides new APIs to write into EBDA area
and read from EBDA area based on user input structure.
Change-Id: I26d5c0ba82c842f0b734a8e0f03abf148737c5c4
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/21536
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
This patch provides a kconfig option as EARLY_EBDA_INIT to
ensures user can make use of EBDA library even during early
boot stages like romstage, postcar.
Change-Id: I603800a531f56b6ebd460d5951c35a645fbfe492
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/21388
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Boards with CBMEM_TOP_BACKUP=y can also use POSTCAR_STAGE
for MTRR setup after adding this file in the build.
Change-Id: I5f9a673ff59ccfbba16308d27f653f5cf3b49017
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/21445
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Postcar failed when loading from stage_cache, if
romstage did not pass same pcf->stack on normal
and resume paths.
Change-Id: I853afb1fbdb942fd671d89950911c850c96e3af3
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/21444
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The deprecation of late (post-romstage) CBMEM initialization was
announced in this blog post:
https://blogs.coreboot.org/blog/2017/05/08/announcing-coreboot-4-6/
There are two warnings:
* In LATE_CBMEM_INIT's help text, I've added a multi-line warning, that
aims to explain the problem.
* In src/mainboard/Kconfig (just below the mainboard selection), there's
a warning which points the user at LATE_CBMEM_INIT, if such a board is
selected.
Also update the function that needs to be implemented, as pointed out by
Keith Hui and Kyösti Mälkki.
Change-Id: I2d21a6ab2fc2811d44fc4febb05841bb2f8d1857
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/21112
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
We now require EARLY_CBMEM_INIT and romstage_handoff to
support HAVE_ACPI_RESUME. Thus acpi_handoff_wakeup() would
never call an externally defined acpi_get_sleep_type().
Name _sleep_type() was also inapproriate here, as it referred
to hardware-dependent SLP_TYP field of PM1CNT but still
returned ACPI_Sx value instead.
Change-Id: I8dc130f1e86dd7e96922d546f0ae9713188336cd
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/21397
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
It's arch specific, so no need to pollute non-x86 with it.
Change-Id: I99ec76d591789db186e8a33774565e5a04fc4e47
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://review.coreboot.org/21392
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
There is at least one I2C device (being used by Soraka) that has 3
controls -- enable, reset and stop. If the stop gpio is not put into
the right state when turning off the device in suspend mode, then it
causes leakage. Thus, we need control in power resource to be able to
stop the device when entering suspend state.
BUG=b:64987428
TEST=Verified on soraka that touchscreen stop is correctly configured
on suspend.
Change-Id: Iae5ec7eb3972c5c7f80956d60d0d3c321bbefb0f
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/21249
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Provide a new function that will allow adding arbitrary properties
to devicetree entries without needing a custom driver for the device.
This will allow the 'generic i2c' driver to support kernel drivers
that need additional device properties exposed and have those board
specific properties set with values from devicetree.
BUG=b:63413023
TEST=not used yet, compiles cleanly
Change-Id: Id272256639a8525406635e168a3db5ab1ba4df6b
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/21269
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Add a Kconfig option to change the \PR.CPxx name string. This
provides some flexibility when working with table not generated
by coreboot.
Change-Id: Ibc0c56783c6da80501e2177de96a414b592cb74f
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/21210
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Split `i2c.h` into three pieces to ease reuse of the generic defi-
nitions. No code is changed.
* `i2c.h` - keeps the generic definitions
* `i2c_simple.h` - holds the current, limited to one controller driver
per board, devicetree independent I2C interface
* `i2c_bus.h` - will become the devicetree compatible interface for
native I2C (e.g. non-SMBus) controllers
Change-Id: I382d45c70f9314588663e1284f264f877469c74d
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/20845
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Move the FSP-specific call for tearing down cache-as-RAM out of
postcar.c and replace it with an empty weak function.
This patch omits checking if (IS_ENABLED(CONFIG_FSP_CAR)). The
temp_ram_exit.c file with the real fsp_temp_ram_exit() is only built
when CONFIG_FSP_CAR is true.
Change-Id: I9adbb1f2a7b2ff50d9f36d5a3640f63410c09479
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/20965
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
If all strings in SMBIOS table are empty, smbios_string_table_len
function should return 2, cause every table must end with "\0\0".
Also replace "eos" field type in smbios structures
from char to u8.
Change-Id: Ia3178b0030aa71e1ff11a3fd3d102942f0027eb1
Signed-off-by: Konstantin Aladyshev <aladyshev22@gmail.com>
Reviewed-on: https://review.coreboot.org/20840
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Julius Werner