Commit Graph

17706 Commits

Author SHA1 Message Date
Duncan Laurie 8a14c39ac6 soc/intel/common: Add LPSS I2C driver
Add a generic LPSS I2C driver for Intel SOCs that use the Synopsys
DesignWare I2C block and have a similar configuration of that block.

This driver is ported from the Chromium depthcharge project where it
was ported from U-Boot originally, though it looks very different now.
From depthcharge it has been modified to fit into the coreboot I2C
driver model with platform_i2c_transfer() and use coreboot semantics
throughout including the stopwatch API for timeouts.

In order for this shared driver to work the SOC must:

1) Define CONFIG_SOC_INTEL_COMMON_LPSS_I2C_CLOCK_MHZ to set the clock
speed that the I2C controller core is running at.

2) Define the lpss_i2c_base_address() function to return the base
address for the specified bus.  This could be either done by looking
up the PCI device or a static table if the controllers are not PCI
devices and just have a static base address.

The driver is usable in verstage/romstage/ramstage, though it does
require early initialization of the controller to set a temporary base
address if it is used outside of ramstage.

This has been tested on Broadwell and Skylake SOCs in both pre-RAM and
ramstage environments by reading and writing both single bytes across
multiple segments as well as large blocks of data at once and with
different configured bus speeds.

While it does need specific configuration for each SOC this driver
should be able to work on all Intel SOCs currently in src/soc/intel.

Change-Id: Ibe492e53c45edb1d1745ec75e1ff66004081717e
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/15101
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-09 17:06:05 +02:00
Duncan Laurie ec00968f08 device: i2c: Add support for I2C bus operations
In order to support doing bus operations on an I2C device that is
described in the devicetree there needs to be some linkage of the
device and the existing opaque I2C controller bus number.

This is provided in a similar fashion to the existing SMBUS operations
but modified to fit within the existing I2C infrastructure.

Variants of the existing I2C helper functions are provided that will
obtain the bus number that corresponds to this device by looking for
the SOC-provided I2C bus operation structure to provide a function
that will make that translation.

For example an SOC using a PCI I2C controller at 0:15.0 could use:

soc/intel/.../i2c.c:
  static int i2c_dev_to_bus(struct device *dev)
  {
    if (dev->path.pci.devfn == PCI_DEVFN(0x15, 0))
      return 0;
    return -1;
  }
  static struct i2c_bus_operation i2c_bus_ops = {
    .dev_to_bus = &i2c_dev_to_bus
  }
  static struct device_operations i2c_dev_ops = {
    .ops_i2c_bus = &i2c_bus_ops
    ...
  }

With an I2C device on that bus at address 0x1a described in the tree:

devicetree.cb:
  device pci 15.0 on # I2C0
    chip drivers/i2c/sample
      device i2c 1a.0 on end
    end
  end

That driver can then do I2C transactions with the device object
without needing to know that the SOC-specific bus number that this
I2C device lives on is "0".

For example it could read a version value from register address 0
with a byte transaction:

drivers/i2c/sample/sample.c:
  static void i2c_sample_enable(struct device *dev)
  {
    uint8_t ver;
    if (!i2c_dev_readb(dev, 0x00, &ver))
      printk(BIOS_INFO, "I2C %s version 0x02x\n", dev_path(dev), ver);
  }

Change-Id: I6c41c8e0d10caabe01cc41da96382074de40e91e
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/15100
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-09 17:05:40 +02:00
Lee Leahy 72179fad42 soc/intel/quark: Pass serial port address to FSP
Pass the serial port address to FSP using a UPD value in the MemoryInit
API.

TEST=Build and run on Galileo Gen2

Change-Id: I86449d80310b7b34ac503ebd2671a4052b080730
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/15079
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-06-09 17:02:26 +02:00
Xing Zheng 96fbc31027 rockchip: rk3399: Add support i2s
This patch enable and configure the clocks and IOMUX for i2s audio path,
and the i2s0 clock is from CPLL.

Please refer to TRM V0.3 Part 1 Chapter 3 CRU, P126/P128/P144/P154/P155
for the i2s clock div and gate setting.

BRANCH=none
BUG=chrome-os-partner:52172
TEST=boot kevin rev1, press ctrl+u and hear the beep voice.

Change-Id: Id00baac965c8b9213270ba5516e1ca684e4304a6
Signed-off-by: Martin Roth <martinroth@chromium.org>
Original-Commit-Id: 9c58fa7
Original-Change-Id: I130a874a0400712317e5e7a8b3b10a6f04586f68
Original-Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/347526
Original-Commit-Ready: Wonjoon Lee <woojoo.lee@samsung.com>
Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://review.coreboot.org/15034
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-06-08 23:27:01 +02:00
Vadim Bendebury 8f8cf4d336 gru: kevin: enable EC SPI interface
This configures and enables SPI interface #5 used for EC
communications on Gru/Kevin.

BRANCH=none
BUG=chrome-os-partner:51537
TEST=with the appropriate depthcharge change it is possible to trigger
     booting Chrome OS from the SD card by pressing '^U' on Gru
     keyboard at the right time.

Change-Id: I5304bf47e030c0b9b7794752f30ffdca6c03a4f4
Signed-off-by: Martin Roth <martinroth@chromium.org>
Original-Commit-Id: b5cc177
Original-Change-Id: I99883daa60562ccddfaeb858c1957d497f05a501
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/346632
Reviewed-on: https://review.coreboot.org/15032
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-06-08 23:22:54 +02:00
Vadim Bendebury 9ed93cb5d5 gru: kevin: configure board GPIOs
Set board GPIOs as required and add their description into the
appropriate section of the coreboot table, to make them available to
depthcharge.

BRANCH=none
BUG=chrome-os-partner:51537
TEST=with the rest of the patches applied it is possible to use
     keyboard on Gru, which indicates that the EC interrupt GPIO is
     properly configured. The rest of the pins will be verified later.

Change-Id: I5818bfe855f4e7faa2114484a9b7b44c7d469727
Signed-off-by: Martin Roth <martinroth@chromium.org>
Original-Commit-Id: e02a05f
Original-Change-Id: I82be76bbd3211179e696526a34cc842cb1987e69
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/346631
Reviewed-on: https://review.coreboot.org/15031
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-06-08 23:21:55 +02:00
Julius Werner 221fdd8cce veyron: Add exception_init() to romstage
I'm not even sure how this slipped through... looks like it had never
been there in the first place. Anyway, on ARM exceptions should always
be reinitialized in all stages to make sure the handlers are still
around (especially in an OVERLAP_VERSTAGE_ROMSTAGE board like this one).

Change-Id: Ic74ea1448d63b363f2ed59d9e2529971b3d32d9a
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/15099
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-06-08 23:21:18 +02:00
Vadim Bendebury 5554d1cf8a rk3399: add ability to configure SPI5
This defines mux settings for the GPIO bank responsible for SPI
interface #5.

BRANCH=none
BUG=chrome-os-partner:51537
TEST=with the rest of the patches applied it is possible to
     communicate with the EC on gru: pressing Ctrl-U during boot
     allows to start Chrome OS from the SD card.

Change-Id: Ibc2293b5662892f7b275434f9a672ef68edf4f9e
Signed-off-by: Martin Roth <martinroth@chromium.org>
Original-Commit-Id: 4f92452
Original-Change-Id: Idf55c069b05492f8cdc204a8c273e39a19a3aef3
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/346630
Original-Tested-by: Shunqian Zheng <zhengsq@rock-chips.com>
Reviewed-on: https://review.coreboot.org/15030
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-06-08 23:20:18 +02:00
Vadim Bendebury 993dbe1fc8 gru: kevin: define GPIOs used on both platforms
The same GPIOs are used on both platforms, definitions are added an a
new .h to make it easier to re-use them across the code.

BRANCH=none
BUG=chrome-os-partner:51537
TEST=panel backlight still enabled on Gru as before. The rest of the
     GPIOs are used in the upcoming patches.

Change-Id: If06f4b33720ab4bf098d23fb91322bba23fe6e90
Signed-off-by: Martin Roth <martinroth@chromium.org>
Original-Commit-Id: c587880
Original-Change-Id: I1a6c5b5beb82ffcc5fea397e8e9ec2f183f4a7e0
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/346219
Original-Tested-by: Shunqian Zheng <zhengsq@rock-chips.com>
Reviewed-on: https://review.coreboot.org/15029
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-06-08 23:19:32 +02:00
Stefan Tauner 37fcd58ba6 inteltool: handle unsafe dumping of graphics registers
The current implementation from Vladimir simply dumps 1 MB of memory
contents starting at the base address of the second PCI device (which
most likely is the VGA controller on Intel systems). This locks up a
number of different systems, e.g. my Ibex Peak-based T410s.

This patch documents the issue and stops dumping the graphics registers
for the -a/--all parameter.

Change-Id: I581bdc63db60afaf4792bc11fbeed73aab57f63a
Signed-off-by: Stefan Tauner <stefan.tauner@gmx.at>
Reviewed-on: https://review.coreboot.org/14627
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2016-06-08 22:35:57 +02:00
Alexandru Gagniuc 6a587343a9 drivers/intel/fsp2.0: Add semantic patch for FspUpdVpd.h header
Previous FSP implementations in coreboot have included FspUpdVpd.h
directly, along with with efi headers. Instead of taking that
approach in FSP 2.0, we provide a semantic patch that, with minimal
modifications, makes FspUpdVpd.h easier to include in coreboot, and
eliminates reliance on external headers and definitions.

Change-Id: I0c2a6f7baf6fb50ae22b64e08e653cfe1aefdaf9
Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc@intel.com>
Reviewed-on: https://review.coreboot.org/13331
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-08 22:35:18 +02:00
Hannah Williams 0f61da8582 soc/apollolake: Add SOC specific c-state table
Please refer Apollolake BIOS Writers Guide

Change-Id: I5f82cdc4b34a53b5184ef1e918cae15a1df6cc5e
Signed-off-by: Hannah Williams <hannah.williams@intel.com>
Reviewed-on: https://review.coreboot.org/15051
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
2016-06-08 22:31:27 +02:00
Hannah Williams f8daa37861 soc/intel/common: Add common code for acpi c/p/t-state entries
Change-Id: I87505bb31cd1b46d27cc5c9ba8d086df7393653e
Signed-off-by: Hannah Williams <hannah.williams@intel.com>
Reviewed-on: https://review.coreboot.org/15050
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-08 22:30:58 +02:00
Ravi Sarawadi 5f8cdc641b mainboard/intel/amenia: Enable VIRT_DEV_SWITCH
Enable virtual dev switch config.

BUG=None
TEST= On Dev FW screen, press SPACE key to boot to normal mode

Change-Id: I0fba36ed85025e4d17da106978dcc88497afee09
Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com>
Reviewed-on: https://review.coreboot.org/15080
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-08 22:25:22 +02:00
Zhao, Lijian 1c6c5836bd Intel/amenia: Make the device address more readable
Use central header file to include device address and interrupt
line to avoid confusion.

Change-Id: I9560031d9f6e12c665c8ae12f7028a67b6c8c904
Signed-off-by: Zhao, Lijian <lijian.zhao@intel.com>
Signed-off-by: Rohit Ainapure <rohit.m.ainapure@intel.com>
Reviewed-on: https://chromium.devtools.intel.com/7248
Tested-by: N, Harshapriya <harshapriya.n@intel.com>
Reviewed-by: Petrov, Andrey <andrey.petrov@intel.com>
Reviewed-on: https://chromium.devtools.intel.com/7580
Reviewed-by: N, Harshapriya <harshapriya.n@intel.com>
Tested-by: Petrov, Andrey <andrey.petrov@intel.com>
Reviewed-on: https://review.coreboot.org/15083
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-08 22:23:53 +02:00
Martin Roth bc46ac5c7d SeaBIOS: Add option to include a bootorder file in cbfs
Including the SeaBIOS bootorder file seems to be a fairly common desire,
so let's make it easy.

Change-Id: Ib0874dee46215287b09c0b52648072ef3ff06ec5
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/15076
Tested-by: build bot (Jenkins)
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2016-06-08 19:17:04 +02:00
Chris Ching b14693193c adi/rc-dff: Add Initial implementaion
* Add ADI vendor

Copy Intel Mohon Peak mainboard to ADI vendor. No functional changes,
only string and ifdef names changed.

Change-Id: I25a6d0ec549c79a8ff149d39f72648f625dc36fe
Signed-off-by: Chris Ching <chingcodes@google.com>
Reviewed-on: https://review.coreboot.org/14778
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-06-08 18:49:52 +02:00
Jan Tatje b8743080d8 mainboard/lenovo/x220: Clean up code
thermal.h still has references to X230 in include guard since it
seems to have been copied from that port. Code formatting changes
in romstage.c.

Change-Id: Id8bd931bed127036e8bb4ab604d9d6145f767e56
signed-off-by: Jan Tatje <jan@jnt.io>
Reviewed-on: https://review.coreboot.org/15071
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>
2016-06-08 18:49:16 +02:00
Antonello Dettori 75c37058b3 cbfstool: Allow to easily build the individual tools
Adds a label for each tool included in the cbfstool package
in order to build them more easily through Make.

Change-Id: Id1e5164240cd12d22cba18d7cc4571fbadad38af
Signed-off-by: Antonello Dettori <dettori.an@gmail.com>
Reviewed-on: https://review.coreboot.org/15075
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-08 18:47:49 +02:00
Jagadish Krishnamoorthy 00f21c7724 mainboard/google/reef: Configure sd card pins
Since the sd card cmd, data, cd lines are configured
as native mode, allow the native controller to control
the termination.
Configure SDCARD_CLK_FB which is used for calibrating the
timing of the actual clock buffer.

BUG==chrome-os-partner:53747
TEST=verify sd card detection

Change-Id: I56611826afb4fb32fefa7f1e4ba19ca4f30ba578
Signed-off-by: Abhay Kumar <abhay.kumar@intel.com>
Signed-off-by: Jagadish Krishnamoorthy <jagadish.krishnamoorthy@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/348377
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/15096
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins)
2016-06-08 16:11:54 +02:00
Arthur Heymans 7d38fafd96 lenovo/x60: add hda_verb.c
This creates a config for the x60 audio based
on values taken from vendor bios.

The pin config is stored in (for linux 4.5 at least):
/sys/class/sound/card0/hw*/init_pin_configs
In the left column there is the pin number.
In the right column there is the default configuration of that pin.
(This has to be done while running the proprietary bios)

More information on the sound card can be found in:
/proc/asound/card0/codec#*
This also hold the information of /sys/class/sound/

What is improved:
- internal microphone is chosen by default
- when jack is inserted it is chosen instead of internal speaker

Before this had to be done manually in alsa or pulseaudio.

TEST= check if internal microphone is used by default in
pavucontrol if you are using pulseaudio.
Plug in a jack with headphones and check if there
is sound output through these and not the build-in
speaker.

Change-Id: Id3b700fd84905a72cc1f69e7d8bfa6145f231756
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/15063
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-06-08 14:10:32 +02:00
Martin Roth 09b6444b88 Makefile: Make printall target more readable
- Put each piece of data from the printall target on its own line.
- Add a blank line between each section.

Change-Id: I50068690ab6795b7ef211865f3798c87debf2a07
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/15077
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-06-07 23:31:17 +02:00
Shaunak Saha f7f1244bc6 intel/amenia: Add asl code to enable google ChromeEC
This patch adds asl code to include support for Google ChromeEC.
We need this to show the battery icon and notifications like charger
connect/disconnect etc.

BUG = 53096
TEST = Plug/Unplug AC Adapter multiple times and make sure the battery
       connected is charging properly.

Change-Id: Id908f145789402573ea54fc4f15cf7a0e651ebf4
Signed-off-by: Shaunak Saha <shaunak.saha@intel.com>
Reviewed-on: https://review.coreboot.org/14987
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2016-06-07 19:39:50 +02:00
Shaunak Saha f6118c62a4 google/reef: Add asl code to enable google ChromeEC
This patch adds asl code to include support for Google ChromeEC.
We need this to show the battery icon and notifications like charger
connect/disconnect etc.

BUG = 53096
TEST = Plug/Unplug AC Adapter multiple times and make sure the battery
       connected is charging properly.

Change-Id: I06f48eda894418514c8ed0136500fff0efd12a35
Signed-off-by: Shaunak Saha <shaunak.saha@intel.com>
Reviewed-on: https://review.coreboot.org/15069
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2016-06-07 18:31:20 +02:00
jongpil19.jung d841da8512 Kevin/Gru : Update Board ID table.
Add board id table as kevin/gru configuration.

BUG=chrome-os-partner:53519
BRANCH=chromeos-2016.02
TEST=check boot on Kevin board.

Change-Id: I30c16916f3cda0ac88d2ce5a922e936a405fcc89
Signed-off-by: Martin Roth <martinroth@chromium.org>
Original-Commit-Id: 16c7b5486befd73c3e31624970ba1c97e526676f
Original-Change-Id: Ib69ed9dad8e1a9e08717545c6be19a90e0298c43
Original-Signed-off-by: jongpil19.jung <jongpil19.jung@samsung.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/345736
Original-Commit-Ready: Vadim Bendebury <vbendeb@chromium.org>
Original-Tested-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://review.coreboot.org/15028
Tested-by: build bot (Jenkins)
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-06-07 16:59:07 +02:00
Andrey Petrov e3a8f46c0e soc/intel/apollolake: Add missing DRAM density constants
Add missing constants for DRAM density. This resolves boot issue,
because misconfigured density results in incorrect memory mapping.

Change-Id: I3bad911bf406bfc5677059490d0e89fcbf735b70
Signed-off-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-on: https://review.coreboot.org/15059
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2016-06-07 16:27:17 +02:00
Shunqian Zheng 0d9839b333 rockchip: gru: update the hynix lpddr3 config to run at 928MHz
Update the DDR config and DRAM driver to allow running at up to
928MHz. Kevin config/clock rate are not being changed, but Gru now
runs at 928 MHz.

BRANCH=none
BUG=chrome-os-partner:51537
TEST=booted Kevin and Gru to Linux prompt. Ran stressapptest for 10 min on Gru,

Change-Id: I66c1a171d5c7d05b2878c7bc5eaa0d436c7a1be2
Signed-off-by: Martin Roth <martinroth@chromium.org>
Original-Commit-Id: 8baf0d82816a7ea1c4428e15caeefa2795d001f9
Original-Change-Id: I5e1d6d1025f10203da8f11afc3bbdf95f133c586
Original-Signed-off-by: Shunqian Zheng <zhengsq@rock-chips.com>
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/343984
Original-Reviewed-by: Stephen Barber <smbarber@chromium.org>
Reviewed-on: https://review.coreboot.org/15027
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-06-07 16:14:05 +02:00
Julius Werner 6724b1b6b4 rk3288: Remove duplicate timestamp_init()
Fix bug introduced by merging http://review.coreboot.org/9606 and
http://review.coreboot.org/10740 in the wrong order.

Change-Id: I75dd22cd0cf30c7d91e4fa5171cb482a80eb64ca
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/15070
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-06-06 21:54:34 +02:00
Paul Menzel 517aa8b065 intel/skylake: Fix typo in comment
Correct the spelling of *firmware* in a comment.

Change-Id: I44bcd95f754ff839d582dc2150e1883a6315da9e
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://review.coreboot.org/15078
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-06 21:41:08 +02:00
Kyösti Mälkki 9aba60ed6e pcengines/apu1: Add SMBIOS SKU field
Just the memory size, there is no strap to identify PCB revision.

Change-Id: I65b2f5b0ac6930bead60ea0a551f13a6bcab24c7
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/14997
Tested-by: build bot (Jenkins)
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2016-06-05 10:06:37 +02:00
Hannah Williams 5d9cc7866f soc/apollolake: Put CSE to low power state
fsp_notify(END_OF_FIRMWARE) should be sent to FSP to enable putting CSE
in low power state

Change-Id: I76b8e85ccf077032616ba8e4a333d9264dc65ed2
Signed-off-by: Hannah Williams <hannah.williams@intel.com>
Reviewed-on: https://review.coreboot.org/15054
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-04 23:48:21 +02:00
Alexandru Gagniuc a942bd4952 soc/apollolake/pmc: Store the ACPI bar during set_resources stage
Because the resource for the ACPI BAR is fixed, pci_dev_set_resources
does not store it to the device. This means we need to do part of the
dance to get the ACPI IO region to work after coreboot.

Of course, this BAR can be destroyed later by the OS probing it, but
at least we try to get it working out of coreboot.

Change-Id: Ibff18d30936f94d4f149a89313254531365f43e6
Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc@intel.com>
Reviewed-on: https://review.coreboot.org/15048
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-04 23:46:44 +02:00
Damien Zammit 68e1dcfdd9 nb/intel/x4x: Fix unpopulated value
Previously, 0x0 was the value being used for an unpopulated dimm
on spd[62], however some DDR2 dimms have 0x0 as a valid value.
Now use 0xff which is an unused value even on DDR2/DDR3.

Change-Id: I55a91a6c3fe3733a7bb2abc45ca352c955c07c99
Signed-off-by: Damien Zammit <damien@zamaudio.com>
Reviewed-on: https://review.coreboot.org/15058
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
2016-06-04 23:46:05 +02:00
Kyösti Mälkki 062ef1cca6 AGESA boards: Split dispatcher to romstage and ramstage
The way dispatcher table is set up prevents linker from
optimizing unused code away, we currently have raminit in ramstage.

Optimize this manually by configuring AGESA_ENTRY booleans for
romstage and ramstage separately. This will remove references in
FuncParamsInfo and DispatchTable -arrays.

All boards now include multi-core dispatcher, it has minimal footprint:
  AGESA_ENTRY_LATE_RUN_AP_TASK

ACPI S3 support depends on HAVE_ACPI_RESUME being enabled:
  AGESA_ENTRY_INIT_RESUME
  AGESA_ENTRY_INIT_LATE_RESTORE
  AGESA_ENTRY_INIT_S3SAVE

Disabled for all boards as it was not used:
  AGESA_ENTRY_INIT_GENERAL_SERVICES

Change-Id: I7ec36a5819a8e526cbeb87b04dce4227a1689285
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/14417
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-06-04 23:44:33 +02:00
Omar Pakker a03609b496 intelmetool: Add the X99 ISA Bridge device id
This adds the ISA bridge device id for the Intel C160/X99 series
chipset to the intelmetool.

Change-Id: I2e7db0fe1692985ebb167b9a44ab412a45a9f3bd
Signed-off-by: Omar Pakker <omarpakker+coreboot@gmail.com>
Reviewed-on: https://review.coreboot.org/15053
Tested-by: build bot (Jenkins)
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@googlemail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-06-04 23:41:22 +02:00
Arthur Heymans 7afcfe0f9f gm45: enable setting all vram sizes from cmos
Setting the size of the preallocated memory for the igd is done
using a cmos parameter, gfx_uma_size. This was limited to a subset of
all available sizes, that were already implemented elsewhere
in the northbridge code.

What this does is change the cmos parameter to 4 bits instead
of 3 bits to accomodate all vram sizes.
It also adds a sane default of 32mb that already was in place.
The northbridge code that reads this cmos parameter is
also changed for this new cmos settings.

352M is disabled since it causes issues on systems with 4GB or more ram.

TEST: Build, flash target. Clear cmos by corrupting
the checksum (nvramtool -c something).
Set a desired value in gfx_uma_size using nvramtool.
"dmesg | grep stolen" to see what is actually allocated.

Change-Id: Ia6479d03f1abe6d0c94bd7264365505e8f8eaeec
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/14900
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2016-06-04 23:40:24 +02:00
Kyösti Mälkki 90e63deeba AGESA f12 f15: Add OEM customisation
Follow-up on commits a5d72a3 and 53052fe for f12 and f15.
OEM Hooks are not BiosCallOuts.

Change-Id: Iab22b0d73282a5a1a5d1344397b4430c0ebb81b5
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/14888
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-06-04 11:11:08 +02:00
Kyösti Mälkki 5003632407 AGESA: Fix invalid use of CFG_ declarations
The declarations of CFG_ evaluate to correct values only when
included after the definitions of BLDCFG_ in buildOpts.c.
So we never have CFG_PLAT_NUM_IO_APICS defined here.

Change-Id: I94b3dee5a3207b37921eb24a0bcd73b5a217b2d3
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/14887
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-06-04 11:09:22 +02:00
Kyösti Mälkki 206e157cc1 AGESA: Fix invalid BLDCFG_ and CFG_ use
The definitions of CFG_ would evaluate to incorrect values
when Options.h is included outside buildOpts.c, where all
BLDCFG_ values are defined.

Already done for f16kb.

Change-Id: I5d725b9306027c7c46c6450ab17b692fa948cf5b
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/14886
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
2016-06-04 11:08:13 +02:00
Kyösti Mälkki b97dc871d9 AGESA: Drop unused assembly files
Change-Id: I0a452b6234b02222be82ca8694868e1ffbfceaee
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/14396
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
2016-06-04 11:03:16 +02:00
Kyösti Mälkki 6de9795143 AGESA: Remove unused platform configuration files
Change-Id: Ie6effa802f6971c59b5c4e07ca7d98736e27859f
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/14885
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
2016-06-04 11:02:24 +02:00
Kyösti Mälkki db1b344207 AGESA f10: Pick sample platform configuration
Tree does not have any AGESA f10 boards. Keep the Danube platform
as a sample configuration file for unlikely future use.

Change-Id: I025aff48fcd0884b45e2a0a993d82f317ede48be
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/14884
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
2016-06-04 11:02:06 +02:00
Kyösti Mälkki 11f3443db6 AMD boards: Drop comment on include file
The included file does not declare pm_ioread(), and the
modified file does not call it either.

Change-Id: I9723caf1062db23b4a3648e07c2dc4c02f862619
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/14968
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-06-03 20:12:30 +02:00
Kyösti Mälkki b62c5e8949 aopen/dxplplusu: Disable HW scrubber
See initialize_ecc() for the awful hack that got us around cache-as-ram
being invalidated as we do ECC HW scrubbing. It once worked, but
compiler nowadays puts more registers on the stack.

Not much interest to try fix ECC for this particular board.

Change-Id: Ie6a09e28b0af5bbf2d68af72f5d98c03df33c402
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/15014
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
2016-06-03 20:10:00 +02:00
Lin Huang b497b48027 rockchip: gru: enable eDP display
This patch enables eDP display by:
o. setting HPD pinmux, backlight, vdd for eDP
o. setting vop mode
o. enabling VGA configs for edid

BRANCH=none
BUG=chrome-os-partner:51537
TEST=The dev screen is shown on kevin board

Change-Id: If8b07307454daa88727d317cc208d6c97de07ad7
Signed-off-by: Martin Roth <martinroth@google.com>
Original-Commit-Id: b1ad9337510f5437f691153dc68883edf273e4c7
Original-Change-Id: Id7006619b5be638b286a5402d892a5361ac1e430
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/340026
Original-Reviewed-by: Shunqian Zheng <zhengsq@rock-chips.com>
Reviewed-on: https://review.coreboot.org/14858
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-06-03 18:08:27 +02:00
Shunqian Zheng d1cec75ce8 rockchip: rk3399: initialize display for eDP
This patch adds functions to init the display. To set up the display,
initialize the eDP and read the EDID.  Based on these, we then
set the clock for VOP, and finally enable VOP and backlight.

For a mainboard, it should set the vop_id, vop_mode and
framebuffer_bits_per_pixel in devicetree.cb.

For VOP_MODE_AUTO_DETECT, it will try eDP first and then
HDMI (which is not supported yet).

EDIT: Updated Makefile to only build in new files if
MAINBOARD_DO_NATIVE_VGA_INIT is enabled. All of these
platforms should have it enabled, so this shouldn't make
any difference except now, before the platform code is
in place.

BRANCH=none
BUG=chrome-os-partner:51537
TEST=test with the other patch

Change-Id: If935415026c945ab6ee128bd6bbdd792890aa24a
Signed-off-by: Martin Roth <martinroth@google.com>
Original-Commit-Id: c1020cc806775629f4d5dc57bd805a9a12169386
Original-Change-Id: Ic32d0a251cb8e08aa5f0b15b2c06c4e02c08a761
Original-Signed-off-by: Lin Huang <hl@rock-chips.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/342336
Original-Commit-Ready: Vadim Bendebury <vbendeb@chromium.org>
Original-Tested-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-by: Shunqian Zheng <zhengsq@rock-chips.com>
Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://review.coreboot.org/14857
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-06-03 18:08:10 +02:00
Lee Leahy e747b7473e drivers/intel/fsp1_1: Make weak routines quiet
Now that there is a better way of finding optional routines, make the
weak routines quiet so that it may be used for the optional
implementation.

TEST=Build and run on Galileo Gen2

Change-Id: Ic58c7de216394f80aee3a78dd08bd4682783be42
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/15043
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-03 17:30:34 +02:00
Lee Leahy 287cd7563e mainboard/intel/galileo: Add CREATE_BOARD_CHECKLIST
Select CREATE_BOARD_CHECKLIST to create the checklist for the Quark SOC
and Galileo board.

TEST=Build and run on Galileo Gen2.

Change-Id: Ieb3e9a5a4c149cf160e11d44a515591b57fe5c83
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/15004
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-06-03 17:30:05 +02:00
Lee Leahy fc3741f379 Add Board Checklist Support
Build the <board>_checklist.html file which contains a checklist table
for each stage of coreboot.  This processing builds a set of implemented
(done) routines which are marked green in the table.  The remaining
required routines (work-to-do) are marked red in the table and the
optional routines are marked yellow in the table.  The table heading
for each stage contains a completion percentage in terms of count of
routines (done .vs. required).

Add some Kconfig values:
*  CREATE_BOARD_CHECKLIST - When selected creates the checklist file
*  MAKE_CHECKLIST_PUBLIC - Copies the checklist file into the
   Documenation directory
*  CHECKLIST_DATA_FILE_LOCATION - Location of the checklist data files:
   *  <stage>_complete.dat - Lists all of the weak routines
   *  <stage>_optional.dat - Lists weak routines which may be optionally
      implemented

TEST=Build with Galileo Gen2.

Change-Id: Ie056f8bb6d45ff7f3bc6390b5630b5063f54c527
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/15011
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-06-03 17:29:13 +02:00
Lee Leahy eb0e7bc976 mainboard/intel/galileo: Set board version
Return the correct board version in SMBIOS.

TEST=Build and run on Galileo Gen2

Change-Id: I97ec7bcd475142eb90930152da0244a3c5d09634
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/15041
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-06-03 17:28:23 +02:00