Commit Graph

37607 Commits

Author SHA1 Message Date
Angel Pons ebf800c538 nb/intel/haswell/early_init.c: Remove invalid register writes
MRC does not use the value of SSKPD, and will overwrite it with constant
values at the end of memory initialisation. Since coreboot does not rely
on this particular bit's value, it is safe to drop the writes to set it.

MCHBAR register 0x6120 is undocumented. It is nowhere to be found in any
documentation or code I have access to; not even for Sandy/Ivy Bridge,
the platform where this mysterious register write originally came from.

These workarounds were copied from Sandy Bridge, but do not apply to
Haswell. They were dropped on Broadwell, so drop them for Haswell too.

Tested on Asrock B85M Pro4, still boots.

Change-Id: I21d9656a7595d47ac8648c08d223b7cbafd213c3
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46683
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-24 21:43:10 +00:00
Angel Pons f27662f5ba nb/intel/haswell/finalize.c: Align with Broadwell
Reorder register writes to match the locking order in Broadwell.

Tested on Asrock B85M Pro4, still boots and registers are still locked.

Change-Id: Ibe15c2598fabda752c9a54eba6362621e144ad77
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46682
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-24 20:47:59 +00:00
Angel Pons 6fe3c06614 nb/intel/haswell/finalize.c: Align MC locking with Broadwell
Broadwell uses a 32-bit or, so also use it on Haswell for consistency.
This has no effect because MRC already locks the memory controller down.

Tested on Asrock B85M Pro4, still boots and register is still locked.

Change-Id: Ida69cd9a95a658c24b4d2558dde88b94c167a3f9
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46681
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-24 20:47:27 +00:00
Angel Pons 8cc39a5fae nb/intel/haswell/finalize.c: Lock down MC ARB register
The Haswell System Agent BIOS Spec revision 0.6.0 indicates this
register needs to be locked, and Broadwell already locks it.

Tested on Asrock B85M Pro4, still boots and register is locked.

Change-Id: Icdeb39e2fdde1403b6ab83faed214addca863f4b
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46680
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-24 20:47:17 +00:00
Angel Pons 97f0d81503 nb/intel/haswell/finalize.c: Lock PCU DDR PTM
This register has a lock bit. The Haswell System Agent BIOS Spec
revision 0.6.0 indicates it needs to be set, thus set it. Note that
Broadwell already locks this register.

Tested on Asrock B85M Pro4, still boots and register is locked.

Change-Id: Ie23b825e708edbfc04ec0d7783f868e8632eb608
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46679
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-24 20:46:57 +00:00
Angel Pons 63837b0af0 nb/intel/haswell/finalize.c: Drop obsolete SA PM lock
This register had a lock bit on Sandy Bridge, but does not on Haswell.
Moreover, the bit remains cleared on Asrock B85M Pro4 with coreboot.
Therefore, remove the write to this bit, because it has no effect.

Tested on Asrock B85M Pro4, still boots.

Change-Id: I382a6d69233ced5af069767eb61b56741ed665be
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46678
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-24 20:46:42 +00:00
Angel Pons 385ce9f4f8 nb/intel/haswell/finalize.c: Use PCI register names
Tested with BUILD_TIMELESS=1, Asrock B85M Pro4 remains identical.

Change-Id: I46331225f36a58615c9cb67d6387fd020d30a04d
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46677
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-24 20:46:28 +00:00
Angel Pons f92f27370d soc/intel/broadwell: Use get_{pmbase,gpiobase}
This is to align Broadwell and Lynx Point.

Change-Id: I9facaec2967616b07b537a8e79b915d6f04948a7
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45717
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-24 20:46:11 +00:00
Angel Pons cbcbb6767e sb/intel/lynxpoint: Ensure that `dev->chip_info` is not null
Use either a regular null check or `config_of` to avoid bugs.

Change-Id: I36a01b898c3e62423f27c2940b5f875b73e36950
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46665
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-24 20:45:49 +00:00
Angel Pons 84fa224b53 sb/intel/lynxpoint: Use spaces around `|`
Coding style says so.

Tested with BUILD_TIMELESS=1, Asrock B85M Pro4 remains identical.

Change-Id: I72386bbe4b38602a641bf8dc9448d6a3e95d297a
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46718
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-24 20:43:15 +00:00
Angel Pons 2f30e8ca03 nb/intel/gm45: Clean up header handling
There's no need to have ACPI guards in `gm45.h`, since the only things
the ASL files require are the base address definitions in `memmap.h`.
Also, remove the southbridge include from `gm45.h` and place it only in
the files that actually require something from it.

Tested with BUILD_TIMELESS=1, Roda RK9 remains identical.

Change-Id: Ica2c5ae9f57595c8577a1bfcc3b57f2c57b3e980
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45452
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-24 20:42:32 +00:00
Angel Pons ae2a522827 nb/intel/gm45: Introduce memmap.h
Move all memory map definitions into a separate header.

Tested with BUILD_TIMELESS=1, Roda RK9 remains identical.

Change-Id: Idddb63069b7a0b7b4d6c7850473a71318748bb9b
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45451
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-10-24 20:42:19 +00:00
Angel Pons 3e33be2e69 nb/intel/gm45: Add more DMIBAR/EPBAR registers
Add definitions for more DMIBAR/EPBAR registers, and specify their sizes
as well. Also, expand a comment as the registers' purpose is now known.

Tested with BUILD_TIMELESS=1, Roda RK9 does not change.

Change-Id: I9687d34e0663e70bdd2a1aa682246c2448690e18
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45448
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-24 20:42:07 +00:00
Angel Pons 6642b44b29 nb/intel/ironlake: Add more host bridge PCI IDs
The host bridge PCI device ID can be changed by the firmware. There
is no documentation about it, though. There's 'official' IDs, which
appear in spec updates and Windows drivers, and 'mysterious' IDs,
which Intel doesn't want OSes to know about and thus are not listed.

The current coreboot code seems to be able to change the device ID
of the host bridge, but it seems to be missing a warm reset so that
the device ID changes. Account for the 'mysterious' device IDs in
the northbridge driver, so that booting an OS has a chance to work.

For the sake of completeness, add the PCI device IDs for Clarkdale.
Although only Arrandale is known to work, both of them are Ironlake.

It is possible that the Management Engine handles changing the PCI
device ID, which would not happen when using a broken ME firmware.

Change-Id: I93c9c47e2b0bf13d80c986c7d66b6cdf0e192b22
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45562
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-24 16:30:42 +00:00
Angel Pons 9d7431c848 nb/intel/ironlake: Generalise northbridge chip name
The code is known to work on processors other than just i7's. Also, use
the northbridge's name (Ironlake) in place of the CPU's (Arrandale).

Change-Id: Ia33fa285b4bacd652932d2187384ca1814c9528a
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46664
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2020-10-24 16:29:55 +00:00
Angel Pons 7bbf45ed3f nb/intel/haswell: Generalise northbridge chip name
The code is known to work on processors other than just i7's.

Change-Id: I8be83bf51315547b29ab2b239e953554d3a323a0
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46663
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2020-10-24 15:44:43 +00:00
Angel Pons 76b8bc2201 nb/intel/haswell: Set up Root Complex topology
System BIOS must program some of the Root Complex Topology Capability
Structure registers located in configuration space, specs say. So do it.

Tested on Asrock B85M Pro4, still boots.

Change-Id: Ia2a61706a127bf2b817004a8ec6a723da9826aad
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43744
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-24 15:44:14 +00:00
Angel Pons 72f4dda6b7 sb/intel/lynxpoint/pcie: Fix clock gating routine
The use of `1 < 5` as a bit mask was obviously a typo. Correct it as
`1 << 5` to match what Intel doc #493816 (Lynx Point PCH BWG) states.

Change-Id: I85734a68a42ec65b124d68514039a1dda7946adc
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45713
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-24 14:03:54 +00:00
Kevin Chiu d3318cfe49 mb/google/zork: update USB 2.0 controller Lane Parameter for berknip
Enhance USB 2.0 C0/C1 A0/A1 SI by increasing the level of
"HS DC Voltage Level" and " Disconnect Threshold Adjustment" registers.
COMPDISTUNE0: 0x3->0x7
TXVREFTUNE0: 0x6->0xf

BUG=b:166398726
BRANCH=zork
TEST=1. emerge-zork coreboot
     2. check U2 register is set correctly.
     3. U2 SI all pass

Change-Id: I69d942605c6d43ece0d71f67df3a5e00b998219b
Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46545
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-24 14:00:08 +00:00
Michael Niewöhner 062b92ef65 cpu/intel/common: rework code previously moved to common cpu code
Rework the code moved to common code in CB:46274. This involves
simplification by using appropriate helpers for MSR and CPUID, using
macros instead of plain values for MSRs and cpu features and adding
documentation to the header.

Change-Id: I7615fc26625c44931577216ea42f0a733b99e131
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46588
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-10-24 09:53:26 +00:00
Michael Niewöhner 10ae1cf2cd {cpu,soc}/intel: deduplicate cpu code
Move a whole bunch of copy-pasta code from soc/intel/{bdw,skl,cnl,icl,
tgl,ehl,jsl,adl} and cpu/intel/{hsw,model_*} to cpu/intel/common.

This change just moves the code. Rework is done in CB:46588.

Change-Id: Ib0cc834de8492d59c423317598e1c11847a0b1ab
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46274
Reviewed-by:  Felix Singer <felixsinger@posteo.net>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-24 09:46:45 +00:00
Angel Pons 29a52c8308 soc/intel/broadwell: Add ECC config reporting
This has been taken from Haswell, and is just to reduce differences.

Change-Id: Ib872cbcd20d6e212b1f55400aa350dc6ba44dc2a
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46367
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-10-23 20:29:28 +00:00
Angel Pons 162a737599 soc/intel/broadwell: Remove unnecessary array
The MAD_DIMM registers can be read within the loop just fine.

Change-Id: Id0c79aaa506f7545826445bc5b065408105b46ba
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46369
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-10-23 20:29:07 +00:00
Angel Pons 973c9d45ad soc/intel/broadwell: Fix copy-pasted copy-paste error
The code with this error was copy-pasted from Haswell. It was fixed with
commit dab81a4 (northbridge/intel/haswell: Fix copy paste error) for
Haswell. Do the same for Broadwell. Given that LP SKUs only support one
DIMM per channel, this change makes no difference in practice.

Change-Id: I2a7bee617354870aa4334b6c0e6b49d831e64c23
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46366
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2020-10-23 20:28:42 +00:00
Angel Pons 430f1c5764 soc/intel/broadwell: Align raminit-related code with Haswell
Use Haswell MCHBAR register names and align cosmetics of functions.

Tested with BUILD_TIMELESS=1, Purism Librem 13 v1 remains identical.

Change-Id: Ie8f369a704b833da86c2eb5864dffe2e8c4bb466
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46364
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-23 20:28:28 +00:00
Angel Pons 239c966e48 soc/intel/broadwell: Relocate `report_memory_config` function
This allows us to make it static, like it is on Haswell.

Change-Id: I8f782ce6ac390082c56a881c6b26d82b548205d9
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46360
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-10-23 20:28:02 +00:00
Angel Pons 0a9ac9f4fb soc/intel/broadwell/romstage/pch.c: Drop reg-script usage
Change-Id: I0e83eb724edc41514928482afe1bc90fb782e852
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46359
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-10-23 20:27:49 +00:00
Angel Pons 7a957543b5 soc/intel/broadwell/romstage/romstage.c: Clean up includes
Tested with BUILD_TIMELESS=1, Purism Librem 13 v1 remains identical.

Change-Id: Ibbffe152e511065dc265155555c56446fbb70405
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46358
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-23 20:27:21 +00:00
Shaunak Saha 84275161a9 mb/google/volteer: Add settings for noise mitgation
Enable acoustic noise mitgation for volteer platforms.

BUG=b:153015585
BRANCH=none
TEST= Measure the change in noise level by changing the values
in devicetree.

Signed-off-by: Shaunak Saha <shaunak.saha@intel.com>
Change-Id: I69a6453091bf607d3c5847c99bc077e6b7dbc639
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45053
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-23 20:26:33 +00:00
Shaunak Saha 0d0f43f9d3 soc/intel/tigerlake: Add Acoustic features
Expose the following FSP UPD interface into coreboot:
- AcousticNoiseMitigation
- FastPkgCRampDisable
- SlowSlewRateFor

BUG=b:153015585
BRANCH=none
TEST= Measure the change in noise level by changing the UPD values.

Signed-off-by: Shaunak Saha <shaunak.saha@intel.com>
Change-Id: I1924a3bac8beb16a9d841891696f9a3dea0d425f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45052
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-10-23 20:25:49 +00:00
Angel Pons 7fa445e385 soc/intel/broadwell: Move `fill_postcar_frame` to memmap.c
Other Intel northbridges have this function in this file.

Change-Id: I9f084e760ec438d662484455212b5c40a8448928
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46357
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-10-23 18:14:42 +00:00
Angel Pons cc2708797e soc/intel/broadwell: Drop reg-script usage from bootblock PCH init
Change-Id: I87145215ccec86e391d0dbd9171b08d7fd73ad9a
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46352
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-23 18:14:28 +00:00
Angel Pons ec05de6f54 soc/intel/broadwell: Define RCBA register LCAP
This register has a name. Use it.

Change-Id: I952584c4aa92fc917d2fc0ef174ee12ae3eeee81
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46340
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2020-10-23 18:14:21 +00:00
Angel Pons 9ab02cb5fc soc/intel/broadwell/finalize.c: Use register names
Tested with BUILD_TIMELESS=1, Purism Librem 13 v1 remains identical.

Change-Id: Ida1266f52fcc06577bd876f2cf3e3324ced6ab9d
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46338
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-10-23 18:14:06 +00:00
Angel Pons 67e1d359de soc/intel/broadwell: Sort SA registers in ascending order
Tested with BUILD_TIMELESS=1, Purism Librem 13 v1 remains identical.

Change-Id: Ifc3ac5e1d17d5aa45dc7e912cbc210d89af7cd2b
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46337
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-23 18:13:42 +00:00
Angel Pons ffc505b995 soc/intel/broadwell: Drop reg-script to finalize SA
There's no need to use reg-script to do this. Since Haswell does not use
reg-script, drop it here to ease comparisons between both platforms.

Change-Id: I28323e891661758c23542c23ad9409d7fafbadf6
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46525
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-23 18:13:34 +00:00
Angel Pons 82654b3fe6 nb/intel/haswell/raminit.c: Clean up local variables
Remove unnecessary arrays, use unsigned types for non-negative values
and constify where possible. Also define NUM_CHANNELS and NUM_SLOTS.

Change-Id: Ie4eb79d9c48194538c0ee41dca48ea32798ad8c6
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46363
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-23 18:13:17 +00:00
Angel Pons a0cb713ce2 soc/intel/broadwell: Revise SA lockdown sequence
The MC_LOCK register was written twice and SA PM no longer has a lock
bit. Update the sequence as per the Broadwell BIOS Specification, but
keep the registers sorted by type.

Change-Id: I91cd0aa61ba6bc578c892c1a5bc973bf4c28d019
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46324
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-23 18:12:17 +00:00
Angel Pons 8cb8374e3c sb/intel/lynxpoint: Drop space after casts
Casts can be considered unary operators, so drop the space.

Tested with BUILD_TIMELESS=1, Asrock B85M Pro4 remains identical.

Change-Id: Ib180c28ff1d7520c82d2b5a5ec79d288ac8b0cf3
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46528
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by:  Felix Singer <felixsinger@posteo.net>
2020-10-23 18:10:51 +00:00
Angel Pons 5d92aa5882 haswell/broadwell: Fix typos of `BCLK`
Change-Id: Ifed3c8250d5c9869493285d0b87580b70ff37965
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46373
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by:  Felix Singer <felixsinger@posteo.net>
2020-10-23 18:10:30 +00:00
Angel Pons 9f3bc37102 nb/intel/sandybridge: Correct designation of MRC version
Do not use `System Agent version` to refer to the MRC version, which is
what the register being printed contains under normal circumstances.

Change-Id: I8679bae37b8ccb76e9e9fc56fc05c399f6030b29
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46372
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-10-23 18:10:20 +00:00
Angel Pons 7f454e4cbd nb/intel/haswell: Correct designation of MRC version
Do not use `System Agent version` to refer to the MRC version, which is
what the register being printed contains under normal circumstances. Use
the code from Broadwell, which also happens to be indented with tabs.

Change-Id: I03b24a8e0e8676af7c5297dc3fc7bf60b9bbb088
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46371
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-10-23 18:10:12 +00:00
Angel Pons 1ca6b531ee nb/intel/haswell: Drop ASM to call into MRC
Commit c2ee680 (sandybridge: Use calls rather than asm to call to MRC.)
did it for Sandy Bridge, and this commit does it for Haswell.

Tested on Asrock B85M Pro4, still boots with MRC.

Change-Id: Ic915ae2a30f99805b2c87df8f9a9586a74a40c29
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46370
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-10-23 18:09:51 +00:00
Angel Pons 0117e4eae3 nb/intel/haswell: Constify pointers to strings
Jenkins complains about it.

Change-Id: I20abdd01ca2b93e8a4de31664ff48651e7268d25
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46368
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-10-23 18:09:41 +00:00
Angel Pons 6791ad221b nb/intel/haswell: Make MAD_DIMM_* registers indexed
This allows using the macro in a loop, for instance.

Change-Id: Ice43e5db9b4244946afb7f3e55e0c646ac1feffb
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46362
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-10-23 18:09:32 +00:00
Angel Pons 6fe7986daf nb/intel/haswell: Drop unnecessary register read
Reading MAD_CHNL has no effect, so there's no need to read it here.

Change-Id: I8d2aa4787de7f54f49d161f61c9c0abaa811cb83
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46361
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-10-23 18:09:12 +00:00
Angel Pons ac02814478 soc/intel/broadwell/memmap.c: Use `SA_DEV_ROOT` macro
Tested with BUILD_TIMELESS=1, Purism Librem 13 v1 remains identical.

Change-Id: I013357d31974582f64a35b8228d9edfa16af99fd
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46356
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by:  Felix Singer <felixsinger@posteo.net>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-10-23 18:09:04 +00:00
Angel Pons dd558fd0cf soc/intel/broadwell: Use common early SMBus code
Disabling interrupts and clearing errors was being done twice, once in
the `smbus_enable_iobar` reg-script, and another in `enable_smbus`.

Change-Id: I58558996bd693b302764965a5bed8b96db363833
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46355
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-10-23 18:08:51 +00:00
Angel Pons f2e2b9688e soc/intel/broadwell/lpc.c: Drop reg-script usage for PCH misc init
Change-Id: I4846f9303367452bbb1d21c2d7f4a1fb9f2efe5d
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46351
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-10-23 18:08:13 +00:00
Angel Pons 2436ac037b soc/intel/broadwell/lpc.c: Drop reg-script usage for PCH PM init
Change-Id: I570fedc538a36f49912262d95b7f57ad779dc8a5
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46350
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-10-23 18:07:35 +00:00