Commit Graph

29647 Commits

Author SHA1 Message Date
Nitheesh Sekar f371b051b0 qcs405: Update bootblock size
Increase the size of bootblock from 96K to 128K.

Change-Id: Ifc6e7239ed2978a8490fa229945ebd5ed9182298
Signed-off-by: Nitheesh Sekar <nsekar@codeaurora.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33159
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-06-21 08:48:42 +00:00
Philip Chen 3970a9d964 mb/google/hatch: Do not pull down GPP_F2 internally
There is already an external pull-up/down resistor tied to
this pin to identify if the board is single-channel or
dual-channel memory SKU.

BUG=b:135496271
BRANCH=none
TEST=build

Signed-off-by: Philip Chen <philipchen@google.com>
Change-Id: Ie218657fd9dde113ab26cf5551d1dff1b6e392b6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33583
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-06-21 08:47:07 +00:00
Christian Walter f70cb8bf96 soc/intel/skylake/romstage: Increase size of postcar stack
I increase the size oof the postcar stack to prevent a stack overflow
during the measured boot feature. After common string functions have
been moved from inline into .c file
(https://review.coreboot.org/c/coreboot/+/32901), I experienced a stack
overflow in the postcar stage while verifiying the romstage during
measured boot. To prevent this, the stack size should be increased. To
play it safe, it should be increased to 8 KiB - though this is open for
discussion.

Change-Id: I6f1a4631bcadfb8c7d1de5bf0919e40990a65606
Signed-off-by: Christian Walter <christian.walter@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33434
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-06-21 08:46:48 +00:00
Arthur Heymans bf1da4b449 x86/smmstub: Fix compiling with external toolchains
This copies the makefile code from the smm/smm.o.

Now works with clang version 7.0.1 from my OS using
CONFIG_ANY_TOOLCHAIN.

Change-Id: I298d24d54b8fb27da96257ccda65b7fbee988ebb
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/30504
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-06-21 08:45:30 +00:00
Hsin-Hsiung Wang fd54acf098 mediatek/mt8183: set vproc12 voltage correctly
The correct address for vproc12 register of sw mode is 0x1426 instead
of 0x140a.

BUG=b:80501386
BRANCH=none
Test=Boots correctly on Kukui and see that regulator is not stuck to
1.05V anymore:
grep vproc12 /sys/kernel/debug/regulator/regulator_summary

Change-Id: I13867b11c44019875e0ed607343197950a3b38b2
Signed-off-by: Hsin-Hsiung Wang <hsin-hsiung.wang@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33168
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-06-21 08:44:53 +00:00
Nico Huber 6d7564cdfe Move -Wlogical-op into xcompile
Clang doesn't know `-Wlogical-op`, so let's move it into xcompile where
we can easily distinguish between the two. However, this requires us to
split out `GCC_ADAFLAGS*` from `GCC_CFLAGS*`.

Change-Id: I6a50de0bc5372f61337f237383d32645ba86b0fd
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33579
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-06-21 08:44:49 +00:00
Arthur Heymans c82d7e76d5 mb/lenovo/x201/smihandler.c: Remove useless smihandler code
This code to handle the brightness from SMM is copied from the Lenovo
Thinkpad X60 code, but does not work on later generation. The PCI
device it tries to address does not even exist on those devices.

Change-Id: I0c25c3e5bec651b27158a84cc91289639a04ceb6
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33508
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-06-21 08:44:24 +00:00
Arthur Heymans 2c0ecc1f83 mb/packardbell/ms2290/Kconfig: Remove ARCH_x options
Those are already selected in cpu/intel/model_2065x/Kconfig.

Change-Id: I7421faa24b8a95d2780bce0651cde0bfeb357833
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33507
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-06-21 08:43:57 +00:00
Arthur Heymans 4c0d5cbb87 mb/*/{x201,packardbell}: Remove unused C-state generation functions
Those are copied from Lenovo X60 code, but are unused.
NOTE: No ACPI C-state are generated on this platform but Linux has a
separate driver for that.

Change-Id: Ie9b49f5451d8cde9c36672cac1f0f14cb3f0095e
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33140
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-06-21 08:43:03 +00:00
Arthur Heymans 04326aabcd sb/intel/ibexpeak/smihandler: Move finalizing to a common location
TODO: There is no reason to do this in SMM.

Change-Id: I8bbb2f65bbe674bd1bc4ae8a4086bd1f5e9a79fa
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33139
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-06-21 08:42:36 +00:00
Frans Hendriks 7c05d2a641 security/tpm/Makefile.inc: Remove VBOOT dependency for tss files in postcar
tss_marshaling.c and tss.c depends on VBOOT for postcar.
Eltan vendorcode used function in these file, but has VBOOT disabled.

Remove depency of VBOOT for postcar fo tss/tcg-2.0/tss-marshaling.c and
tss/tcg-2.0/tss.c

BUG=N/A
TEST=Created binary and verify logging on Facebook FBG-1701

Change-Id: I195c79283abf403208f406518372bf52289772ed
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33444
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-06-21 08:41:44 +00:00
Weiyi Lu e621d8f11a mediatek/mt8183: Add infra group DCM setting
Add infra group DCM (Dynamic Clock Management) settings,
which slows down OR gate clocks while hardware is in idle state.

BUG=b:80501386
BRANCH=none
TEST=Boots correctly on Kukui.

Change-Id: I4741dfb7b984deb92171f370e5fb2593829d74c2
Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31977
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: You-Cheng Syu <youcheng@google.com>
2019-06-21 08:41:34 +00:00
Hung-Te Lin f6317b4892 src/driver/vpd: Update vpd_decode from upstream
The upstream vpd_decode.c has been revised to prevent overrun of decoded
contents.

BUG=chromium:967209
TEST=select VPD config on kukui; make; boots on at least kukui boards.

Change-Id: I1a50670a66b7b174d2a432c29d90152b86c32982
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33414
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-06-21 08:41:16 +00:00
Mario Scheithauer aa5e8e099e siemens/mc_apl5: Change PTN interface settings
Switch the default clock output for single LVDS mode to odd bus only.

Change-Id: I278e761566a112d95cbd6c79e09c076d70b93e8f
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33196
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2019-06-21 08:40:16 +00:00
Mario Scheithauer 37fedc0414 siemens/mc_apl5: Enable TPM support
This patch enables TPM on SPI and adds the needed devicetree entry for
mc_apl5.

TEST=Build coreboot for mc_apl5 board and check the TPM console output.
In addition the TPM was correctly verified by our Linux driver.

Change-Id: Iafc967c7a2bfee9bdb9b6591d12328620e2887cc
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33173
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-06-21 08:40:08 +00:00
Mengqi Zhang fbeec122c0 google/kukui: Increase SPI flash speed to boot faster
Increase SPI flash speed from 26MHz to 56MHz and set correct tick_dly
to get faster boot process.

BUG=b:80501386
BRANCH=none
TEST=emerge-kukui coreboot; emerge-elm coreboot

Change-Id: I8f44883b4f4a198146330caf5420dc39d5592a0a
Signed-off-by: Mengqi Zhang <Mengqi.Zhang@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32462
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-06-21 08:39:23 +00:00
Mengqi Zhang 026be3d76f mediatek: Add SPI tick_dly setting
Add spi tick_dly setting for high-speed spi xfer.

BUG=b:80501386
BRANCH=none
TEST=emerge-kukui coreboot; emerge-elm coreboot

Change-Id: Ie49fc3efe2a4a6dcdf2a2fc4c91b47e35d4f086e
Signed-off-by: Mengqi Zhang <Mengqi.Zhang@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32461
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-06-21 08:38:41 +00:00
Mengqi Zhang 89b1753c22 mediatek/mt8183: Add SPI GPIO driving setting
Set SPI GPIO driving to support SPI FLASH.

BUG=b:80501386
BRANCH=none
TEST=emerge-kukui coreboot; emerge-elm coreboot

Change-Id: I95002ec71abd751c33c089185db04ed4a8686699
Signed-off-by: Mengqi Zhang <Mengqi.Zhang@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32460
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-06-21 08:38:25 +00:00
You-Cheng Syu 4b47e5a851 google/kukui: Enable RTC
Enable RTC so that we can see correct timestamp in CrOS eventlogs.

BUG=b:134461866
TEST='mosys eventlog list' shows correct timestamp on Kukui

Change-Id: Ie9ef7c9343c781e348429cd5376a4a5519641e16
Signed-off-by: You-Cheng Syu <youcheng@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33356
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2019-06-21 08:37:42 +00:00
You-Cheng Syu 10494c497f mediatek/mt8183: Support RTC in ramstage
We need to support RTC in ramstage so that we can see correct timestamp
in ChromiumOS eventlog.

BUG=b:134461866
TEST='mosys eventlog list' shows correct timestamp on Kukui

Change-Id: Idb0fe5c05e4ecdf0e6398e3c781c71d14f85f19b
Signed-off-by: You-Cheng Syu <youcheng@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33355
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-06-21 08:37:32 +00:00
jg_poxu a2c6a09985 mediatek/mt8183: Add efuse calibration in auxadc
The values from auxadc may be incorrect if not calibrated by efuse.
Without calibration, the value error range is about +/-50mv,
and after being calibrated the error range is about +/-10mv.

BUG=b:131391176
TEST=make clean && make test-abuild; boots on Kukui rev 2 units.
BRANCH=none

Change-Id: Iccd6ea0ad810c993f9b62c0974279c960f890e52
Signed-off-by: Po Xu <jg_poxu@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32800
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: JG Poxu <jg_poxu@mediatek.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-06-21 08:37:06 +00:00
Hung-Te Lin 8d83c662c3 google/kukui: Revise FMAP firmware layout
Adjust FMAP sections that
- ELOG only needs 4K (by driver limitation)
- SHARED_DATA only needs 4K or less (for netboot params)
- SMMSTORE is probably not needed since UEFI@ARM is not available yet
- VPD can be smaller (most x86 devices have only 16/8K for RO/RW)
- Increase RW_LEGACY to 1M (recommended value)
- Move all new saved space to CBFS

BUG=b:134624821
TEST=Built Kukui image and boots on Rev2 units.

Change-Id: Id2910df73ea47bfa32e056d631d1c3e5f1eed0d1
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33239
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-06-21 08:35:59 +00:00
Elyes HAOUAS adc3235eb7 cpu/amd/family_10h-family_15h: Fix 'if' condition identical branches
Change-Id: I1c937a62388c38090ee2cc3228973cfb8361bac7
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33257
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2019-06-21 08:35:01 +00:00
Elyes HAOUAS 283b438f5c soc/intel/common/block/pcr: Remove unneded 'else'
'else' is not needed after a 'break' or 'return'.

Change-Id: Ib3371ef6edb85a47ed734dd2ff9ce94008aa4e65
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33336
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Vlado Cibic
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-06-21 08:33:35 +00:00
Elyes HAOUAS c166071beb mb/google/snappy: Remove unneeded 'else'
'else' is not needed after a 'break' or 'return'.

Change-Id: I7b6c319a58b9f4f47de19336d18d00b73d3d3772
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33335
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Vlado Cibic
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-06-21 08:32:57 +00:00
Elyes HAOUAS 1ba0da17c8 ec/kontron/kempld/kempld_i2c.c: Remove unneeded 'else'
'else' is not needed after a 'break' or 'return'.

Change-Id: I0843bebe48e4b91fc76c440ae33bbca838621de9
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33334
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Vlado Cibic
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-06-21 08:32:32 +00:00
Elyes HAOUAS b53427156c ec/google/chromeec/ec_lpc: Remove unneeded 'else'
'else' is not needed after a 'break' or 'return'.

Change-Id: I98d0ab0d139186b312e8c1086c475ba6ef0b7d3b
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33333
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-06-21 08:32:08 +00:00
Elyes HAOUAS 561e11d6f8 drivers/intel/fsp1_0/fastboot_cache: Remove unneeded 'else'
'else' is not needed after a 'break' or 'return'.

Change-Id: I109f5aaa87afde61a36fff884305b43c1de2c680
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33332
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Vlado Cibic
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-06-21 08:31:46 +00:00
Elyes HAOUAS 77b3a91bba arch/x86/rdrand.c: Remove unneeded 'else'
'else' is not needed after a 'break' or 'return'.

Change-Id: Ib7bdefb0027a35de42f6a665b98f9e5a2791061f
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33331
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Vlado Cibic
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-06-21 08:31:19 +00:00
Jacob Garber 698d83a7c8 lib: Prevent memory leak on error path
Free the tree before returning to prevent a leak.

Change-Id: I1132c0e7404eec1af3adc19a83257f28563f8a58
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Found-by: Coverity CID 1401799
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33298
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-06-21 08:31:02 +00:00
Jacob Garber 176670e31a drivers/amd/agesa: Assert that StdHeader is non-null
Coverity believes there is a path where StdHeader is possibly
null. This *should* be incorrect, since the header is actually
initialized through the module dispatch framework, though Coverity
can't see it due to the extensive type-punning. However, the control
flow is so dizzingly complicated that I'm not even completely sure,
so adding an extra assert to be careful won't hurt anyway.

Change-Id: If3d7c5d5c5bba846e7453b3dbc824e2208d749fb
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Found-by: Coverity CID 1379932
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33214
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-06-21 08:30:24 +00:00
Jacob Garber 31755adc5a nb/amd/amdmct/mct: Remove duplicate if condition
The case when Speed == 5 is already dealt with on line 111.

Change-Id: Icc41c00fb333a51001568f588c17f7b6c6a3a923
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Found-by: Coverity CID 1229626
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33213
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-06-21 08:30:00 +00:00
Jacob Garber 19cbe03534 nb/amd/amdmct/mct_ddr3: Remove duplicate conditional
This check is already performed at the beginning of
dct_ddr_voltage_index().

Change-Id: Ia73025333c152f14249afb16d05f66791e69e7cb
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Found-by: Coverity CID 1347322, 1347323
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33264
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-06-21 08:29:45 +00:00
Jacob Garber 86d8c4279d nb/amd/amdmct/mct_ddr3: Remove duplicate code
This conditional is exactly the same as the one right below it, except
the operations are reorganized slightly.

Change-Id: I00c19a467d23a0736bc2a33b516f97080039e634
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Found-by: Coverity CID 1347321
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33267
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-06-21 08:28:53 +00:00
Joel Kitching 532e0c74e1 vboot: relocate code to log and clear recovery mode switch
Logging and clearing the recovery mode switch doesn't have
anything to do with vboot_handoff.  Move it to the main verstage
logic file.

BUG=b:124141368, b:124192753
TEST=make clean && make test-abuild
BRANCH=none

Change-Id: I2e74f3893463e43fe5fad4a8df8036560f34e0db
Signed-off-by: Joel Kitching <kitching@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33534
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-06-21 00:52:35 +00:00
Joel Kitching b6bcb6cc8f vboot: remove functions which read vboot_handoff.out_flags
These functions are no longer used and may be removed:
* vboot_handoff_check_recovery_flag
* vboot_get_handoff_flag

BUG=b:124141368, b:124192753
TEST=make clean && make test-abuild
BRANCH=none

Change-Id: Ie05652ef1288eef74bd2e7e8bea79fd29d523859
Signed-off-by: Joel Kitching <kitching@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33533
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-06-21 00:50:59 +00:00
Joel Kitching a06cd6c29e vboot: remove vboot_handoff_get_recovery_reason
Two functions retrieve vboot recovery_reason:
* vboot_handoff_get_recovery_reason
* vboot_get_recovery_reason_shared_data

Previously, when CBMEM comes online, a vboot_handoff data
structure is created, and depending on the architecture,
coreboot may eventually lose access to vboot_working_data.

After implementing vboot_working_data CBMEM migration,
vboot_working_data is always guaranteed to be accessible.

vboot_get_recovery_reason_shared_data is corrected to also
allow accessing vboot_working_data in ramstage and postcar.

Now, vboot_handoff_get_recovery reason returning a valid recovery
reason implies that vboot_get_recovery_reason_shared_data should
*also* return a valid recovery reason.  Thus we may remove the
former.

BUG=b:124141368, b:124192753
TEST=make clean && make test-abuild
BRANCH=none

Change-Id: Iac216dc968dd155d9d4f8bd0f2dfd5034762f9a0
Signed-off-by: Joel Kitching <kitching@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33532
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-06-21 00:50:48 +00:00
Hsin-Hsiung Wang c10af299ae mediatek/mt8183: Calibrate vsim2 to 2.7 V
The default voltage of vsim2 is set to 2.76V for sim card usage.
In general, 2.76V of vsim2 is composed of 2.7V main voltage and 0.06V calibration voltage.
However, vsim2 is used for the tx_ovdd power of display port IT6505 on the kukui board design which needs 2.7V.
So we set it to 2.7V with modifying calibration value.

BUG=b:126139364
BRANCH=none
TEST=measure vsim2 voltage with multimeter

Change-Id: I4dffdde89cbde91286d92e6c2b445f0b3d0ad2fe
Signed-off-by: Hsin-Hsiung Wang <hsin-hsiung.wang@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32057
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-06-21 00:06:02 +00:00
Frans Hendriks 863853cd2d soc/intel/braswell/smbus.c: Add support for i2c mode block write
Intel Braswell supports i2c block write using SMBus controller.

smbus_i2c_block_write() is added to configure SMBus controller in i2c
mode before calling do_i2c_block_write().

Add smbus.c to ramstage.

BUG=N/A
TEST=Verify LCD display is working on Facebook FBG-1701

Change-Id: I50c1a03f624b3ab3b987d4f3b1d15dac4374e48a
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33225
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-06-20 15:41:37 +00:00
Frans Hendriks e48be35bca southbridge/intel/common/smbus: Add do_i2c_block_write()
Intel Braswell supports i2c block writes using SMBus controller.
This support is missing in actual smbus routines.

Add do_i2c_block_write() which is a based on do_smbus_block_write() but
also write first byte to SMBHSTDAT1.
The caller needs to configure the SMBus controller in i2c mode.

In i2c mode SMBus controller will send the next sequence:
SMBXINTADD, SMBHSTDAT1, SMBBLKDAT .. SMBBLKDAT

To ensure the the command is send over the bus the SMBHSTCMD register must
be written also

BUG=N/A
TEST=Config eDP for LCD display on Facebook FBG-1701

Change-Id: I40f8c0f5257a62398189f36892b8159052481693
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/30800
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-06-20 15:25:51 +00:00
Aamir Bohra b09de70eda mb/google/hatch: Remove unused USB2 port5 from baseboard devicetree
Hatch newer board revision do not use USB port5 for discrete BT.
Hence remove the port configuration and UBS2 P5 asl entry. The older
board version would continue to use USB2 P5 hence moved the entry to
overridetree.cb

Change-Id: I98297d6b81e3184b7b0a14710f3790f5df30d68b
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33060
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2019-06-20 08:48:54 +00:00
sridhar 685b377e7e mb/intel/whl_rvp: Configure FSP UPDs of DDI ports for whlrvp
This patch configures FSP UPD values for HPD and DDC of DDI ports for
WHLRVP.

BUG=none
TEST=Tested that eDP & DP works on WHLRVP

Signed-off-by: Usha P <usha.p@intel.com>
Signed-off-by: sridhar <sridhar.siricilla@intel.com>
Change-Id: I576469f5564e3e56159762752dbe4557e9dc1912
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33435
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-06-19 19:35:56 +00:00
Elyes HAOUAS ba5f318736 sb/nvidia/ck804/fadt.c: Remove unused LONG_FADT
LONG_FADT is not used at all. So remove it and use sizeof(acpi_fadt_t) for
header length.

Change-Id: I433d1b2e0f3b9505d7c52eb14f1a476fbe52a284
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33436
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Lance Zhao <lance.zhao@gmail.com>
2019-06-19 19:35:05 +00:00
Elyes HAOUAS 0c5666828d {mb,sb}: Use get_acpi_table_revision(FADT)
Change-Id: Id3d7f021a52e08906ae0a3f794756e397601fe96
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33428
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-06-19 19:34:10 +00:00
Arthur Heymans f957201cf0 sb/intel/common/spi: Properly check if setting FRP succeeded
Change-Id: Ib0b63c3b0342c62aeabb5c6e418eb9811fc6597d
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33389
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-06-19 19:33:06 +00:00
Raul E Rangel 1264d64a74 grunt: Change Bayhub eMMC base clock to 200MHz
The clock was previously set to 52MHz to workaround the fact that
depthcharge didn't support tuning.

Tuning has now been enabled in depthcharge:
https://chromium-review.googlesource.com/c/chromiumos/platform/depthcharge/+/1655553

BUG=b:122244718
TEST=Verified on grunt that it speeds up boot by 130ms

Change-Id: If847cea2a7848bcd175958db86e652d4f710201a
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33430
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2019-06-19 19:29:35 +00:00
Marshall Dawson ce2b2bad77 util/amdfwtool: Update for Family 17h
Add arguments for additional PSP blobs needed with Family 17h support,
including the new AGESA binary loaders.

Create a new type of structure and entry for a BIOS directory table,
containing PMU code, microcode updates, as well as the BIOS initial
code.

Details on each of these items may be found in the AMD Platform Security
Processor BIOS Architecture Design Guide for AMD Family 17h Processors
(NDA only, #55758).

BUG=b:126593573
TEST=Used with WIP Picasso

Change-Id: I4899dedb6f5e29a27ff53787a566d5b8633a8ad5
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33400
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2019-06-19 19:14:39 +00:00
Elyes HAOUAS 3f347a1379 lib/spd_bin.c: Remove unused include <arch/byteorder.h>
Change-Id: Ifb8171e559c5c8081597291ffefabc676c7fa5e1
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33538
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-06-19 12:30:04 +00:00
Elyes HAOUAS b79a04c716 src/mainboard: Remove unused include <arch/byteorder.h>
Change-Id: I3d638febddbd88cd4870795f96dd1bbf123c7ba3
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33537
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-06-19 12:29:18 +00:00
Peter Lemenkov 22230687aa mb/lenovo/*/romstage: Remove unused include byteorder.h
Change-Id: I3e500aafd26b7524a6782883b9a30f55b544102d
Signed-off-by: Peter Lemenkov <lemenkov@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33511
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-06-19 12:28:24 +00:00