Commit Graph

28338 Commits

Author SHA1 Message Date
YH Lin 967edec254 flapjack: get sku_id from ec (cbi)
On flapjack, retrieve the board information via CBI interface.

Also reserving 0x2 sku_id for the case of un-provisioned board as this is the id
used prior to the readiness of cbi.

BUG=b:123676982
BRANCH=kukui
TEST=provisioned cbi info and verify the sku_id.

Signed-off-by: YH Lin <yueherngl@google.com>
Change-Id: Iad7a52df38e2045abbdded8ba0a1f1544de961fc
Reviewed-on: https://review.coreboot.org/c/31586
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-02-26 11:18:40 +00:00
Patrick Rudolph 6220f8d833 soc/cavium/cn81xx: Enable RNG for DRAM init
The Cavium DRAM init might use the RNG for pattern generation.
Initialize it before running DRAM init.

Tested on OpenCellular Elgon.
The RNG generates non identical numbers.

Change-Id: I886f920e9941793fb76b56cc5a24a42e23b082e0
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/31567
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-02-26 11:18:18 +00:00
Qii Wang d569845964 mediatek/mt8183: Modify I2C source clock
This patch change i2c source clock to TOPCKGEN.

BUG=b:80501386
BRANCH=none
TEST=Boot correctly on kukui.

Change-Id: I49e0acda22dba449d0873a95ba5fae79a9cef569
Signed-off-by: Qii Wang <qii.wang@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/31519
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2019-02-26 11:15:41 +00:00
Rizwan Qureshi 747154074c soc/intel/cannonlake: Update GPIO definitions for Virtual GPIO
Denote appropriate reserved groups as virtual GPIOs in Cannonlake LP/H SoC.

Change-Id: I4da161b91f83749b0ae29b387b5c99c1c3f706d8
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-on: https://review.coreboot.org/c/31552
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-02-26 11:15:05 +00:00
Werner Zeh db561e6e39 acpi: Sort the reported APIC-IDs in the MADT table
coreboot performs MP-Init in a parallel way. That leads to the fact
that the order, in which the CPUs are woken up, can vary from boot to
boot. The creation of the MADT table just parses the devicetree and
takes the CPUs reported there as it is for creating the single local
APIC entries. Therefore, the OS will see different order of CPUs.
There are CPUs out there (like Apollo Lake for example) which have
shared caches on core-level and if the order is random this can end up
in assigning cores to different tasks or even OSes (in a virtual
environment) which uses the same cache. This in turn will produce
performance penalties across these distributed tasks/OSes.

Though there is a way to discover the core- and cache-topology it will
in the end be necessary to take the APIC-ID into account. To simplify
it, one can achieve the same output by sorting the APIC-IDs in an
ascending order. This will lead to the fact that CPUs that share a given
cache will be reported right next to each other in the MADT.

Change-Id: Ida74f9f00a4e2a03107a2124014403de60462735
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/31545
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2019-02-26 11:14:49 +00:00
Werner Zeh bd660e2338 commonlib: Add Bubble sort algorithm
Add an implementation for Bubble sort. For now, only integers can be
sorted in an ascending or descending order. It can be later simply
extended to cover other datasets like strings if needed.

The reasons for choosing bubble sort are:
* it is a simple algorithm
* bubble sort is stable, i.e. it does not exchange entries which are not
  needed to be sorted as they are already in order

Change-Id: I2c5e0b5685a907243b58ebe6682078272d316bf6
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/31544
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-02-26 11:14:41 +00:00
Matt DeVillier 38b6ccfed9 payloads/tianocore: default to MrChromebox's working branch
Rather than attempt to maintain patches against upstream Tianocore, use
MrChromebox's coreboot framebuffer branch as the default build target.

Rework the Makefile to default to MrChromebox's coreboot_fb branch, but
also allow for aribitrary commits from upstream Tianocore to be used
as build targets.

Ensure the branch is synced on each build, as long as working directory
is clean, and that switching between commits or trees is handled sanely.

Eliminate TIANOCORE_MASTER as a selectable build target, since unpatched
it is unlikely to boot on any device. It can easily be specified via
the 'revision' option if desired.

Test: build for the default stable target, for upstream/master
as the specified revision, and for an arbitrary valid commit hash.

Change-Id: I4a83db3cd64c7d5b652c6e95780d10051f143e88
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/31543
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-02-26 11:13:11 +00:00
Ronak Kanabar da7ffb48b2 soc/intel/common: Include cometlake PCH IDs
Add cometlake specific PCH IDs

Change-Id: I18dda48cee29213aa66c0ccddf3da31f0f489d2f
Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-on: https://review.coreboot.org/c/31234
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-02-26 02:17:25 +00:00
Philipp Deppenwiese 66f9a09916 security/vboot: Add measured boot mode
* Introduce a measured boot mode into vboot.
* Add hook for stage measurements in prog_loader and cbfs.
* Implement and hook-up CRTM in vboot and check for suspend.

Change-Id: I339a2f1051e44f36aba9f99828f130592a09355e
Signed-off-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/29547
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-02-25 22:29:16 +00:00
Patrick Rudolph bacd57dfaf cpu/x86/smm: Add qemu's SMM-Revision Level
The SMI handler on qemu returned early, due to missing SMM-Revision
Level support.

Add the ID qemu uses, which is AMD64 compatible for qemu-system-x86_64.

Fixes booting tianocore payload with SMM variable store on qemu.

Change-Id: I978b94150cfc49a39c2a0818eb14a649850e451d
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/c/31594
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2019-02-25 11:21:53 +00:00
Mike Banon 749fe1eef9 src/device/Kconfig: Change default VESA mode from 117h to 118h
Change default VESA/native framebuffer mode (needed for bootsplash and
graphical framebuffer console) from 117h (1024x768 64k-color (5:6:5))
to 118h (1024x768 16.8M-color (8:8:8)) mode.

This provides console output at Lenovo G505S even if e.g. GRUB is the
payload, while it is unlikely to cause any downsides for the other
boards.

Signed-off-by: Mike Banon <mikebdp2@gmail.com>
Change-Id: Ia348199bbd430532b1399706dd84490c9680b5f5
Reviewed-on: https://review.coreboot.org/c/31595
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-02-25 11:21:19 +00:00
Elyes HAOUAS e2af9b8481 ACPI: Enum only used ACPI tables
enum contained redundant names and wasn't exhaustive anyway.

Change-Id: I4d74ff61c555c5953932efbd7edccfd3157cb5be
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/31592
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-02-25 11:20:35 +00:00
Damien Zammit f0a9128424 intelmetool: Use GPLv2+ where possible
Upstream intelmetool is out of date; I suggest I archive it
instead of trying to merge coreboot's changes into it.

However I would like to preserve the licensing of files in the tool
as GPLv2+ where possible instead of GPLv2-only.

Change-Id: I47b1ff2734f54c65f4214b39244bd868ef44b83c
Signed-off-by: Damien Zammit <damien@zamaudio.com>
Reviewed-on: https://review.coreboot.org/c/31587
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2019-02-25 11:19:37 +00:00
Patrick Rudolph b94ecc4e69 soc/cavium/common: Make ecam0_get_bar_val common
Move ecam0_get_bar_val into the common folder and make it public.
Compile it for romstage and ramstage.

To be used by romstage PCI code.
Tested on OpenCellular Elgon.

Change-Id: I18b1ede56795bf8c1f9476592291b8ea610eccd4
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/31566
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-02-25 11:18:32 +00:00
Elyes HAOUAS 99850600d0 sb/amd/hudson/acpi: Fix illegal object references
Issue spotted using IASL 20190215 on mainboard GIZMOSPHERE_GIZMO2:
"Object is created temporarily in another method and cannot be accessed"

Change-Id: I1e4ca2c765083db3a27e415d3a69bef0912a606b
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/31554
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-02-25 11:17:54 +00:00
Duncan Laurie a213ed659a ec/google/wilco: Fix ACPI power status events
This change fixes the power status events for AC and battery
events from the EC.  The register that was being used is not
returning the expected information.

BUG=b:125472740
TEST=enable ACPI debug in the kernel and verify that AC and
battery insert/remove are detected properly.

Change-Id: I15f71fcf0ca6aa9438e951865787c9fc273792d8
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/31560
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-02-25 11:17:23 +00:00
Kyösti Mälkki 47b9e457fa AGESA vendorcode: Define libagesa rule just once
No reason to keep this rule in per-family directory.

Change-Id: I6bfc9a277674077774c4cb398f8add5e4fa99c69
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/31509
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-02-25 11:16:52 +00:00
Kyösti Mälkki 423d03c163 soc/amd/common: Fix AmdLateRunApTask()
Third parameter ConfigPtr of the callout is of type
AP_EXE_PARAMS and needs to be passed back to AGESA
with AmdLateRunApTask() call.

Change-Id: I1dad64b955b53bd19363737665235f95aa3d451e
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/27277
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-02-25 11:16:27 +00:00
Werner Zeh d35a4811db vendorcode/siemens: Cache currently opened hwi file name
On every call of hwilib_find_blocks() the CBFS file will be mapped and
the contents are parsed to get the offsets for every single block. This
is not needed if the CBFS file name is the same for the different calls.

This patch adds a storage for the currently opened CBFS file name in
CAR_GLOBAL and checks on each call if the file to open is already open.
If yes, the file will not be mapped again which saves execution time.

Test=Booted mc_tcu3, mc_bdx1 and mc_apl1 and verified that hwinfo.hex
is only mapped once across several following hwilib_find_blocks() calls.
In addition a test was done to ensure that files with different names
get mapped correctly.

Change-Id: Id69e0f6c914c2b8e4551fd8a4fb7d452d176afb3
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/31518
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2019-02-25 05:39:45 +00:00
Patrick Rudolph 87abccdd89 mb/emulation/qemu: Fix fw_cfg file loading
The change bcd84fe "mb/emulation/qemu-i440fx: change file handling"
introduced a regression where it loads only 4 bytes of the
ACPI and SMBIOS table, instead of the whole table.

Load the whole ACPI and SMBIOS table.

Tested on Qemu using GNU/Linux.

Change-Id: Ibacbf7caab9be5f181c12e9dd39a2893b13cf6c9
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/c/31593
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-02-24 11:57:25 +00:00
Ronak Kanabar f606a2f5e6 soc/intel/common: Include cometlake SA IDs
Add cometlake specific SA IDs

Change-Id: I1fbbab8a7797b36a9eacbd1c6a0644466f2fe6b1
Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-on: https://review.coreboot.org/c/31226
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
2019-02-24 04:49:37 +00:00
Ronak Kanabar 128bb2a7ca soc/intel/common: Include cometlake CPU IDs
Add cometlake specific CPU IDs

Change-Id: I75d5b82524c9df1402abf6659d62dbc716c28c30
Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-on: https://review.coreboot.org/c/31143
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
2019-02-24 04:49:25 +00:00
Elyes HAOUAS d8e55350f1 arch/x86/smbios.c: Remove duplicated 'processor_upgrade'
Change-Id: I3500a648631c91f3a0812c7e661440743ed6a1e1
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/31555
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-02-23 14:44:18 +00:00
Maulik V Vaghela 3647e5c151 drivers/intel/fsp2_0: Update dependency of USE_FSP_REPO
USE_FSP_REPO used to rely on SOC_INTEL_COMMON_CANNONLAKE_BASE which was
getting selected for cometlake soc also. Since FSP is not yet upstreamed
for cometlake, compilation was failing due to FSP was not found.

So limiting USE_FSP_REPO option to coffeelake and whiskeylake soc only
and excluding for cometlake.

Change-Id: I5e5d5a9fdf3f5d3e79922e97719e8491aa514cef
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/31530
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
2019-02-23 14:25:31 +00:00
Subrata Banik ab9f64d011 soc/intel/cannonlake: Make few more whitespace proper in MCH name
CB:31547 fixes few whitespace error. Here is few more whitespace clean up.

Change-Id: I69c12a5da4feb48b2bc23874332ab341a559f6e6
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/31563
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2019-02-23 04:45:46 +00:00
Kyösti Mälkki b92853ed56 arch/arm64: Add PCI config support in romstage
Change-Id: I9cc3dc51764f24b986434080f480932dceb8d133
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/31307
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2019-02-22 19:32:36 +00:00
Shelley Chen 26905f70b7 mb/google/hatch: Enable wake from trackpad
For some reason, wake does not currently work from GPP_D21, but IRQs
are working fine from that gpio.  Thus, we have to switch IRQ to
GPP_D21 and wake to GPP_A21, which was previously used for IRQs from
the trackpad.  Additionally, we need to use two gpios for irqs and
wake source at the moment because of b:123967687, where FSP is locking
down PCR and configuring ITSS.  We need to configure the wake source
gpio as inverted and the IRQ gpio as non-inverted until the bug is
resolved.

BUG=b:121212459
BRANCH=None
TEST=run evtest with trackpad
     Use trackpad with ChromeOS UI and make sure it reacts as expected.
     Run powerd_dbus_suspend and press trackpad and make sure DUT
     wakes.

Change-Id: I7b236136befc05c6586d9ba69185ed4b5d385273
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/31533
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-02-22 19:00:50 +00:00
Patrick Rudolph 71c0a94987 drivers/cavium: Add UART PCI driver
Add UART PCI driver in cavium/common/pci.

Tested on opencellular/elgon.
The UART is still initialized and usable in Linux.

Change-Id: I0fa2f086aba9b4f9c6dba7a35a84ea61c5fa64e4
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/30608
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-02-22 12:25:25 +00:00
Caveh Jalali ab77008395 mb/google/poppy/variants/atlas: move WiFi wake to GPP_B7
The latest rev. of the atlas board moves the WiFi wake source from
WAKE# to GPP_B7.  The original GPP_A0 in the device tree is just
wrong.  This also reconfigures DW1 to the GPP_B group so we can use
GPP_B7 as a wake source.

GPP_B7 is still configured as a no-connect in gpio.c, so this doesn't
actually enable WiFi wake.  We'll follow up with another patch to set
up GPP_B7 properly on boards that support it.

BUG=b:122327852
BRANCH=none
TEST=atlas still boots

Change-Id: I1816500dd0ab6186fd51aa6945faf73d00c152fe
Signed-off-by: Caveh Jalali <caveh@chromium.org>
Reviewed-on: https://review.coreboot.org/c/31211
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-02-22 11:10:53 +00:00
Joel Kitching d6f71d03f1 vboot: fix STARTS_IN_BOOTBLOCK/_ROMSTAGE logic
Fix up the logic of when to include VBOOT2_WORK symbols on x86,
which are only needed when VBOOT_STARTS_IN_BOOTBLOCK is enabled.

Also correct the value of the __PRE_RAM__ macro in the case that
VBOOT_STARTS_IN_ROMSTAGE is selected.  In this case, DRAM is
already up and verstage should not be considered pre-ram.

BUG=b:124141368, b:124192753
TEST=Build locally for eve
TEST=util/lint/checkpatch.pl -g origin/master..HEAD
TEST=util/abuild/abuild -B -e -y -c 50 -p none -x
TEST=make clean && make test-abuild
BRANCH=none

Change-Id: Ie51e8f93b99ab230f3caeede2a33ec8b443e3d7a
Signed-off-by: Joel Kitching <kitching@google.com>
Reviewed-on: https://review.coreboot.org/c/31541
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-02-22 11:10:40 +00:00
Alex Feinman 2223cbf7de intelvbttool: Add support for reading vbt from sysfs
VBT on Intel(R) systems is available via sysfs as
    /sys/kernel/debug/dri/0/i915_vbt
However the size of this file reads as 0 causing
intelvbttool to fail. This patch implements incremental reads
with realloc for such cases or whenever the file size is not
available (e.g. reading from stdin).
After this patch is applied, intelvbttool can be used as follows:
    sudo intelvbttool -f /sys/kernel/debug/dri/0/i915_vbt -d

Change-Id: I5d17095a5747550b7115a54a7619b7294a846196
Signed-off-by: Alex Feinman <alexfeinman@hotmail.com>
Reviewed-on: https://review.coreboot.org/c/31531
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-02-22 11:09:58 +00:00
Lukasz Siudut 180ac500fc mb/ocp/monolake: Fix booting issues
We experienced booting issues during FSP-M phase. Applying fix that was
introduced for wedge100s  - 817994c1be (mb/ocp/wedge100s/romstage:
Workaround broken platform state) - helped and systems started to
boot properly.

Signed-off-by: Lukasz Siudut <lsiudut@fb.com>
Change-Id: Ibfbe9d19c7413098c56d1b6131640097fdf731ab
Reviewed-on: https://review.coreboot.org/c/31435
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2019-02-22 11:09:04 +00:00
Jeremy Soller 4185de5ff7 soc/intel/cannonlake: Add support for setting FSP-S PcieRpHotPlug from devicetree
Tested on system76 galp3-c

Signed-off-by: Jeremy Soller <jeremy@system76.com>
Change-Id: I3aa8990a335e413628c016007ebabf7142aef80d
Reviewed-on: https://review.coreboot.org/c/31535
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-02-22 11:08:21 +00:00
Rizwan Qureshi eb503296fc soc/intel/cannonlake: Add ASL function for setting pad mode
Add a function in gpio ASL library to set pad mode.

BUG=b:123350329

Change-Id: I6c683f27ddffc3132001706d1694c71bb5664577
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-on: https://review.coreboot.org/c/31444
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-02-22 11:07:48 +00:00
Joel Kitching 3ba6caf81e Update vboot submodule to upstream master
Updating from commit id a32c930e:
2018-12-28 16:14:08 -0800 - (futility: updater: quirks: Support special released SNOW RO)

to commit id 1e177741:
2019-02-14 05:27:16 -0800 - (vboot: rename VB2_DISABLE_DEVELOPER_MODE)

This brings in 11 new commits.

Change-Id: I59d83de49006a6d081b206716002697d39099aa4
Signed-off-by: Joel Kitching <kitching@google.com>
Reviewed-on: https://review.coreboot.org/c/31542
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-02-22 11:07:20 +00:00
Julius Werner 7e0dea6317 symbols.h: Add macro to define memlayout region symbols
When <symbols.h> was first introduced, it only declared a handful of
regions and we didn't expect that too many architectures and platforms
would need to add their own later. However, our amount of platforms has
greatly expanded since, and with them the need for more special memory
regions. The amount of code duplication is starting to get unsightly,
and platforms keep defining their own <soc/symbols.h> files that need
this as well.

This patch adds another macro to cut down the definition boilerplate.
Unfortunately, macros cannot define other macros when they're called, so
referring to region sizes as _name_size doesn't work anymore. This patch
replaces the scheme with REGION_SIZE(name).

Not touching the regions in the x86-specific <arch/symbols.h> yet since
they don't follow the standard _region/_eregion naming scheme. They can
be converted later if desired.

Change-Id: I44727d77d1de75882c72a94f29bd7e2c27741dd8
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/31539
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2019-02-22 06:44:02 +00:00
Julius Werner 314b5c370b rockchip/rk3399: Fix BL31 bootmem regions
The BL31 on RK3399 is split into multiple segments... the majority goes
into DRAM, but small parts must be put into SRAM and PMUSRAM. With
CB:31123 only the DRAM part was added to memlayout, so the SRAM parts
will not be correctly marked in bootmem and BL31 loading fails the
selfload check. This patch adds the remaining regions to fix the
problem.

Change-Id: Ia0597216c08512c47361a1dc0beb34d022a8994f
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/31538
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ting Shen <phoenixshen@google.com>
2019-02-22 06:43:47 +00:00
Subrata Banik d1dfba4a1a soc/intel/cannonlake: Add whitespace proper in CPU/MCH/IGD name
Change-Id: I33a50e9fc90162c7cb2aa7fbc3887efe9c6ebcde
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/31547
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2019-02-22 04:17:27 +00:00
Duncan Laurie c98e36fec5 Revert "src/drivers/intel/wifi: Add a W/A for Intel ThP2 9260"
This reverts commit 3afb84a245.

Reason for revert: This is causing issues with the PCIe link
and the system is unable to enter S0ix.  Until it can be fixed
in coreboot revert the change here that is not working properly.

BUG=b:124264120

Change-Id: Ia20da9ab560ca35950b4a916667f51e0f541b382
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/31559
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Caveh Jalali <caveh@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-02-22 03:00:30 +00:00
Scott Collyer 4323175818 mb/google/hatch: Make EC software sync enabled by default
EC software sync had been disabled because BIOS was not bundling a
useful EC image. This is no longer required. This CL removes that
change so EC software sync is enabled by default.

BUG=b:124208414
BRANCH=None
TEST=Tested with a system that have a different RW image and verified
that this image was overwritten to the one bundled in the BIOS and
that the EC was running its RW image.

Signed-off-by: Scott Collyer <scollyer@chromium.org>
Change-Id: Ic1ffdb62e9fa2cacb3296cb3807082f23e171ab5
Reviewed-on: https://review.coreboot.org/c/31537
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-02-22 02:57:27 +00:00
Matt DeVillier 460c2c2483 cpu/intel/common: Add newline to set_feature_ctrl_lock() output
Without newline, if IA32_FEATURE_CONTROL already locked, next
console line will be concatenated. If run on a multiple CPUs,
you get multiple lines concatenated.

Change-Id: I5b73ae4cb045973fa3ce07f4d93fda0caadf78eb
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/31532
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-02-21 19:30:56 +00:00
jg_poxu 9e21b2dbd7 mediatek/mt8183: Support gpio eh and rsel setting for I2C
The setting of these registers are only for i2c pin.

BUG=b:80501386
BRANCH=none
TEST=Boot correctly on Kukui

Change-Id: I518ca07645fe55aa55e94e4f98178baa0b74a882
Signed-off-by: jg_poxu <jg_poxu@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/30974
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-02-21 19:27:44 +00:00
Kyösti Mälkki 187e4c4474 timestamp: Move timestamp_should_run() call
Old location caused spurious error messages when
called from APs, where timestamp_add_now() should
do nothing.

Moving the test also makes get_us_from_boot() usable
from APs (assuming cache coherency).

Change-Id: Ice9ece11b15bbe1a58a038cda3d299862e6f822b
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/31524
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-02-21 19:10:45 +00:00
Ronak Kanabar 69a9565339 soc/intel/cannonlake: SoC specific microcode update check
For CFL and WHL, Microcode is being loaded from FIT. Both
supports the PRMRR/SGX feature. If This is supported the FIT
microcode load will set the msr (0x08b) with the Patch id one
less than the id in the microcode binary. This results in
Microcode getting reloaded again in bootblock and ramstage.
Avoid the microcode reload by checking for PRMRR support.
CFL and WHL CPU die are based on KBL CPU so we need to have
this check, where CNL CPU die is not based on KBL CPU so
skip this check for CNL.

BUG=b:124126405
Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com>

Change-Id: I3311a7413d27044f9c819179e5b0cb9a67b46955
Reviewed-on: https://review.coreboot.org/c/31492
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
2019-02-21 19:10:23 +00:00
Nico Huber 16a41ccaa1 sb/intel/bd82x6x: Fix default IRQ mapping
The default mapping was probably copy-pasted from a random
board and disabled some interrupts (by implicitly clearing
some register bits).

We provide a new default mapping with some reasoning, that
tries to be most compatible (i.e. avoids to use PIRQ E-H
that are not shareable on some boards).

The following functions had their interrupt pin disabled
before:

  o SATA 2 (explicitly, no board seems to enable the device)
  o PCIe Root Port #4, #6-#8 (probably by accident)

PIRQs used before this change: A-D, F and H. After this
change: A-D.

Change-Id: I33f82702ea9c1b9c22ce14f01ee630dbf6203362
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/31498
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-02-21 19:10:00 +00:00
Elyes HAOUAS 26071aaadf ACPI: Correct asl_compiler_revision value
Change-Id: I91b54b43c8bb5cb17ff86a6d9afa95f265ee49df
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/31431
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-02-21 19:07:31 +00:00
Elyes HAOUAS 94ad37619f SMBIOS: Fix bios version
Change-Id: I142f08ed3c2704b8fde6d176f23772f5d6b33e85
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/31437
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-02-21 19:07:18 +00:00
Elyes HAOUAS 16d05daffa mb/roda/rk886ex/acpi/superio.asl: Fix copy-paste error on "COMB"
Error spotted using IASL 20190215:
"Object is created temporarily in another method
and cannot be accessed"

Change-Id: I139c5c7b33671e7ed0c04c06fb290e001e57a687
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/31528
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-02-21 19:04:02 +00:00
Elyes HAOUAS c55934db61 mb/roda/rk9/acpi/superio.asl: Fix copy-paste error on "COMB"
Error spotted using IASL 20190215:
"Object is created temporarily in another method
and cannot be accessed"

Change-Id: I7da9dcd68f5eec6383de7370bc8ab35f96a90c06
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/31526
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-02-21 19:03:55 +00:00
Nico Huber 2f7d0543ff Makefile.inc: Keep .asl intermediates
We used .aml as the file extension for preprocessed ASL code. That
file gets overwritten with the compilation results, fix that.

Change-Id: I11a03dfbcebb0fd762da7b27862a7bdb9a581b92
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/31523
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-02-21 16:05:14 +00:00