Commit graph

7 commits

Author SHA1 Message Date
Yinghai Lu
f42e1770f9 make clear_1m_ram.c to support gcc 3 and gcc4
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2141 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2005-12-09 01:58:07 +00:00
Yinghai Lu
c3b3600222 use CONFIG_LB_MEM_TOPK instead 1M hardcode from issue 50
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2139 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2005-12-07 19:02:45 +00:00
Stefan Reinauer
7ce8c54e2b 1201_ht_bus0_dev0_fidvid_core.diff
https://openbios.org/roundup/linuxbios/issue41
Lord have mercy upon us.




git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2118 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2005-12-02 21:52:30 +00:00
Stefan Reinauer
806e146e75 Applying 11_26_car_tyan.diff from Yinghai Lu.
NOTE: This will break the tree so it can be fixed up later



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2115 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2005-12-01 10:54:44 +00:00
Ronald G. Minnich
fb0a64ba77 CAR patch from YH LU
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2096 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2005-11-23 21:01:08 +00:00
Yinghai Lu
13f1c2af8b eric patch
1. x86_setup_mtrr take address bit.
        2. generic ht, pcix, pcie beidge...
        3. scan bus and reset_bus
        4. ht read ctrl to decide if the ht chain
           is ready
        5. Intel e7520 and e7525 support
        6. new ich5r support
        7. intel sb 6300 support.

yhlu patch
	1. split x86_setup_mtrrs to fixed and var
	2. if (resource->flags & IORESOURCE_FIXED ) return; in device.c pick_largest_resource
	3. in_conherent.c K8_SCAN_PCI_BUS


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1982 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2005-07-08 02:49:49 +00:00
arch import user (historical)
6ca7636c8f Revision: linuxbios@linuxbios.org--devel/freebios--devel--2.0--patch-51
Creator:  Yinghai Lu <yhlu@tyan.com>

cache_as_ram for AMD and some intel


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1967 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2005-07-06 17:17:25 +00:00