2 Commits

Author	SHA1	Message	Date
Karthikeyan Ramasubramanian	876cfe0ee2	spd/lp5: Generate initial SPDs for Sabrina SoC ... Mainboards using Sabrina SoC will be using LP5 memory technology. Generate the initial set of SPDs for the existing LP5 memory parts. BUG=b:211510456 TEST=util/spd_tools/bin/spd_gen spd/lp5/memory_parts.json lp5 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Change-Id: Ibb43f26b36460290341c5ffcad1ef5a2ff1647c8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61543 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>	2022-02-10 12:50:19 +00:00
Reka Norman	3aa61136cc	spd: Add lp5 directory with empty memory_parts file ... Add spd/lp5/memory_parts.json with an empty parts list, then run spd_gen to generate the manifests and empty SPD. Generated using: util/spd_tools/bin/spd_gen spd/lp5/memory_parts.json lp5 BUG=b:204284866 TEST=None Change-Id: I0314314130a1ccc58fb5a0416b110e7a86338fd0 Signed-off-by: Reka Norman <rekanorman@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58928 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>	2021-11-05 12:58:32 +00:00