Success return value in DMI functions GetDmiInfoMain(..) and GetType4Type7Info(...) of AGESA vendorcode is "Flag = TRUE".
This results in a failure of init late function:
"agesawrapper_amdinitlate failed: 1"
It happens because TRUE = 1 = AGESA_UNSUPPORTED.
Replacing TRUE with AGESA_SUCCESS (= 0) fixes this problem.
Only family f15tn does not have such bug.
This patch just replaces TRUE with AGESA_SUCCESS, but maybe all DMI functions should be copied from Trinity family?
Tested on Supermicro H8QGI board with 4 AMD Opteron 6234 processors (f15).
Change-Id: I51bf91333c088a825b92d4a44d1ebe4380c8026c
Signed-off-by: Aladyshev Konstantin <aladyshev@nicevt.ru>
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/2070
Reviewed-by: Marc Jones <marcj303@gmail.com>
Tested-by: build bot (Jenkins)
I have issues when AmdReadEventLog function tries to use BiosCallouts interface.
So it is necessary to provide callout pointer to this function.
Change-Id: I4080e5f07d5d28c41688b2a7deff944b7a0f7bf7
Signed-off-by: Aladyshev Konstantin <aladyshev@nicevt.ru>
Reviewed-on: http://review.coreboot.org/2064
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
Reviewed-by: Zheng Bao <zheng.bao@amd.com>
That code will be used to disable the internal GFX card and enable the
external PCIe card.
The following lines from function `rs780_internal_gfx_enable()` are
taken and reversed.
/* Disable external GFX and enable internal GFX. */
l_dword = pci_read_config32(nb_dev, 0x8c);
l_dword &= ~(1<<0);
l_dword |= 1<<1;
pci_write_config32(nb_dev, 0x8c, l_dword);
It has been tested on the M4A785T-M with the following card inside the
PCIe 16x slot:
02:00.0 VGA compatible controller: nVidia Corporation GT218 [GeForce 210] (rev a2)
Change-Id: I7bd412b987fde98c97464175e2c7a384a8f0fb84
Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo@no-log.org>
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/2065
Tested-by: build bot (Jenkins)
This commit enables the external graphics card.
In order to work, the internal graphic card has to be
disabled, that is done in src/device/device.c through:
vga_onboard->ops->disable(vga_onboard);
which calls the RS780 disable operation introduced in the following
commit: "rs780: add .disable pcie_ops"
This commit was tested with and without the following card:
02:00.0 VGA compatible controller: nVidia Corporation GT218 [GeForce 210] (rev a2)
Thanks Aladyshev for the pointer(in the #coreboot IRC channel on Freenode servers):
Dec 20 19:43:32 <Aladyshev> If you list your internal card in devicetree.cb,
coreboot will distinguish external and internal VGA and choose external one
Change-Id: I92e59dffd158db096a6e99d1ef6e2e248fef933c
Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo@no-log.org>
Reviewed-on: http://review.coreboot.org/2067
Tested-by: build bot (Jenkins)
Reviewed-by: Dave Frodin <dave.frodin@se-eng.com>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
If a 3rd party blob option is selected, make sure that it makes the
user select CONFIG_USE_BLOBS as otherwise the build will fail.
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Change-Id: I04429f23137946525c8577dd9c979bd4a0d17cdc
Reviewed-on: http://review.coreboot.org/2080
Reviewed-by: Dave Frodin <dave.frodin@se-eng.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
This just imports a header. We may wish to modify the i2c interface
and/or unify it with the smbus interface we currently have.
Change-Id: I314f3aef62be936456c6c3e164a3db2c473b8792
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/2079
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Fix some minor discrepancies which prevented the MAX77676 from
getting compiled in properly.
Change-Id: Ib29136da6c15a4bdb24926a91729431c507cd209
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/2076
Tested-by: build bot (Jenkins)
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Since these don't seem very generic and depend on the BL1, let's
move them to the CPU-specific Kconfig.
Change-Id: I33059b7db30d35a1853918a580f312e50a3499fa
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/2077
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
This is still a work-in-progress, but it seems to work better than
before and is less complicated...
Change-Id: I6f730d017391f9ec4401cdfd34931c869df10a9e
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/2041
Tested-by: build bot (Jenkins)
Supermicro H8QGI has integrated Matrox G200 16MB DDR2 graphics.
List it in devicetree.cb to mark it as onboard VGA to coreboot.
This change makes menuconfig option "Use onboard VGA as primary video device" work.
Change-Id: Ia6b9f60e3ae705689f22babd544ad6e628a85df1
Signed-off-by: Aladyshev Konstantin <aladyshev@nicevt.ru>
Reviewed-on: http://review.coreboot.org/2042
Tested-by: build bot (Jenkins)
Reviewed-by: Siyuan Wang <wangsiyuanbuaa@gmail.com>
Reviewed-by: Marc Jones <marcj303@gmail.com>
Fix little mistake in get_bus_conf code
Change-Id: I8c09e501082caa0a20266b007c0744630a356de0
Signed-off-by: Aladyshev Konstantin <aladyshev@nicevt.ru>
Reviewed-on: http://review.coreboot.org/2046
Tested-by: build bot (Jenkins)
Reviewed-by: Siyuan Wang <wangsiyuanbuaa@gmail.com>
Reviewed-by: Zheng Bao <zheng.bao@amd.com>
Reviewed-by: Marc Jones <marcj303@gmail.com>
Size of BiosCallouts[] struct can be calculated as:
CallOutCount = sizeof (BiosCallouts) / sizeof (BiosCallouts [0]);
There is no longer need for REQUIRED_CALLOUTS define.
Originally that change was done for AMD Persimmon in
commit d7a696d0f2
Author: efdesign98 <efdesign98@gmail.com>
Date: Thu Sep 15 15:24:26 2011 -0600
Persimmon updates for AMD F14 rev C0
without deleting the define. This was ported to some of the other
boards and for some the define was not removed.
The AMD Inagua, Parmer and Thatcher boards were already adapted but
the define was left in. So just remove it for those.
Tested on Supermicro H8QGI.
Change-Id: Ia09795579a1170fa20ab94a30feb1af6821153d2
Signed-off-by: Aladyshev Konstantin <aladyshev@nicevt.ru>
Reviewed-on: http://review.coreboot.org/2049
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martin@se-eng.com>
Reviewed-by: Marc Jones <marcj303@gmail.com>
Since SB800, USB2.0 debug port is dev 0x12, func 2.
Change-Id: Ie0e33cb2f0833b0baeef81323e1a0634242fbe55
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Signed-off-by: zbao <fishbaozi@gmail.com>
Reviewed-on: http://review.coreboot.org/1880
Tested-by: build bot (Jenkins)
Reviewed-by: Dave Frodin <dave.frodin@se-eng.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
Reviewed-by: Marc Jones <marcj303@gmail.com>
H8QGI board has 2 IO-APICS with 56 IRQ’s:
IOAPIC[0]: GSI 0-23 - SB700 southbridge
IOAPIC[1]: GSI 24-55 - RD890 northbridge
`gDefaultApicDeviceInfoTable[]` structure in northbridge code
vendorcode/amd/cimx/rd890/nbIoApic.c
has IO-APIC interrupt mapping for HT and IOMMU set to last 31
IRQ pin (24+31=55).
CONST APIC_DEVICE_INFO gDefaultApicDeviceInfoTable[] = {
// Group Swizzling Port Int Pin
{0, 0, 31}, //HT
{0, 0, 31}, //IOMMU
[…]
Also the same value (55) can be found in original Supermicro BIOS ACPI DSDT.
Change-Id: Ie26da1f773716d1b7f5f5f884050ae799afc0b7e
Signed-off-by: Aladyshev Konstantin <aladyshev@nicevt.ru>
Reviewed-on: http://review.coreboot.org/2047
Tested-by: build bot (Jenkins)
Reviewed-by: Zheng Bao <zheng.bao@amd.com>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
GNU CC coverage needs free() and it's highly desirable to leave
the code as genuine as possible.
Change-Id: I4c821b9d211ef7a8e7168dc5e3116730693999c6
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/2051
Tested-by: build bot (Jenkins)
Reviewed-by: David Hendricks <dhendrix@chromium.org>
We ship it in the 3rdparty repository.
Change-Id: Ida52bc7e813f8468910c4ea7838ebb863c52b88a
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/2060
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Tested-by: build bot (Jenkins)
While "payload none" is undesirable for instant flashing,
assume that it was a conscious user choice.
(more immediate: jenkins isn't happy with escape sequences)
Change-Id: I9958b34a037b4d10bb7dba893335a63917623a70
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/2055
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Initialize the pointer fadt to NULL to prevent a later comparison
(if (fadt == NULL)) when the pointer had the *possibility* of never
having been initialized.
Change-Id: Ib2a544c190b609ab8c23147dc69dca5f4ac7f38c
Signed-off-by: Martin Roth <martin@se-eng.com>
Reviewed-on: http://review.coreboot.org/2037
Reviewed-by: Peter Stuge <peter@stuge.se>
Tested-by: build bot (Jenkins)
Add prefix coreboot_ to let make clean find it and delete it.
Change-Id: Ieba9c0e7ca3d2afec311d64159b22746ba5825c4
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Signed-off-by: zbao <fishbaozi@gmail.com>
Reviewed-on: http://review.coreboot.org/2029
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Add configuration for AMD's IMC ROM and fan registers for cimx/sb800
platforms.
- Allows user to add the IMC rom to the build and to configure the
location of the "signature" between the allowed positions.
- Allows for no fan control, manual setup of SB800 Fan registers, or
setup of the IMC fan configuration registers.
- Register configuration is done through devicetree.cb. No files need
to be added for new platform configuration.
- Initial setup is for Persimmon, but may be extended to any cimx/sb800
platform.
Change-Id: Ib06408d794988cbb29eed6adbeeadea8b2629bae
Signed-off-by: Martin Roth <martin@se-eng.com>
Reviewed-on: http://review.coreboot.org/1977
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-by: Marc Jones <marcj303@gmail.com>
The file generated when the IMC or XHCI binaries are included in the rom
was named $(obj)/hudson_romsig.bin. The problem with this is that it
doesn't get deleted when the user does a make clean.
changing the name to coreboot_hudson_romsig.bin makes this happen.
Change-Id: I19a40042fbf0f7b5633d7b35339c05ed90d3243b
Signed-off-by: Martin Roth <martin@se-eng.com>
Reviewed-on: http://review.coreboot.org/1978
Tested-by: build bot (Jenkins)
Reviewed-by: Zheng Bao <zheng.bao@amd.com>
Reviewed-by: Marc Jones <marcj303@gmail.com>
There was already a special case for the SPI base address in
lpc_set_resources for southbridge/amd/cimx/sb800 and
southbridge/amd/agesa/hudson, but it needed to be modified
to keep from killing the IMC rom during initialization. As
soon as the BAR is disabled by setting the new base address,
the IMC dies. The fix is to make sure it's still enabled
when setting the new base address instead of setting the new
address then re-enabling it.
Change the name SPIROM_BASE_ADDRESS to SPIROM_BASE_ADDRESS_REGISTER
to more accurately describe what we're using.
Change-Id: I216d75b722c4332c239d487111a9880eabf59e91
Signed-off-by: Martin Roth <martin@se-eng.com>
Reviewed-on: http://review.coreboot.org/1975
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
The SB800 and Hudson now support adding the IMC ROM which runs from the same
chip as coreboot. When the IMC is running, write or erase commands sent to
the spi bus will fail, and the IMC will die. To fix this, we send a request
to the IMC to stop fetching from the SPI rom while we write to it. This
process (in one form or another) is required for writes to the SPI bus while
the IMC is running.
Because the IMC can take up to 500ms to respond every time we claim the
bus, this patch tries to keep the number of times we need to do that to a
minimum. We only need to claim the bus on writes, and using a counter for
the semaphore allows us to call in once to claim the bus at the beginning
of a number of transactions and it will stay claimed until we release it
at the end of the transactions.
Claim() - takes up to 500ms hit
claim() - no delay
erase()
release()
claim() - no delay
write()
release()
Release()
Change-Id: I4e003c5122a2ed47abce57ab8b92dee6aa4713ed
Signed-off-by: Martin Roth <martin@se-eng.com>
Reviewed-on: http://review.coreboot.org/1976
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
cbfstool was called with the wrong parameters
Change-Id: I405d0fd7c84b46da3c98a36fd19ef0034dc175cf
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/2022
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
With driver-y going away, the current driver code didn't get
compiled in with upstream.
Change-Id: I9bff45a35c995888a482bdc22a1573f6bfb88211
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/2027
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
This is the minimal set of sources that allow the board to build.
These need to be filled in with actual code. But if we get these in upstream
we can stop working against a WIP patch.
Change-Id: I9347a573bb40761f6a12be3ee8febe3ca4be55a3
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-on: http://review.coreboot.org/2018
Tested-by: build bot (Jenkins)
and disable IO mapped UARTs on ARMV7 per default
Change-Id: I712c4677cbc8519323970556718f9bb6327d83c8
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/2021
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Tested-by: build bot (Jenkins)
... to fit into the naming convention
Change-Id: I4a7d81c4d6674d001fc831df863bd2343f6c636f
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/2020
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Tested-by: build bot (Jenkins)
When we need i2c for this cpu we will use the coreboot
smbus code.
Change-Id: I4ba4cc9ae10e5ca830d621ee9c8d9f7bd2129e2f
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-on: http://review.coreboot.org/2019
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
The max include file is in src/drivers/power.
Change-Id: I2e663b472cade17fc50edbb449c0e54fd4a991eb
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-on: http://review.coreboot.org/2017
Tested-by: build bot (Jenkins)
Reviewed-by: David Hendricks <dhendrix@chromium.org>
This file builds fine without including arch/types.h
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Change-Id: Icd38cf429576a2a1a33ebca84389526feddfc169
Reviewed-on: http://review.coreboot.org/2015
Tested-by: build bot (Jenkins)
Reviewed-by: David Hendricks <dhendrix@chromium.org>
stddef.h should be fairly generic across all platforms we'd want to
support, so let's move it to generic code.
Change-Id: I580c9c9b54f62fadd9ea97115933e16ea0b13ada
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-on: http://review.coreboot.org/2007
Tested-by: build bot (Jenkins)
The first ARMv7 CPU we're going to support is the Exynos 5250
used in the Google Snow ChromeBook.
Change-Id: I4de8433bbc6202eb8fef2556a11186a3376d411b
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-on: http://review.coreboot.org/2004
Tested-by: build bot (Jenkins)
Samsung SoC files, including Exynos5 (a Cortex-A15
implementation). Since this is an SoC we'll forego the x86-style
{north,south}bridge and cpu distinction. We may try to split some
stuff out before the final version if prudent.
Change-Id: Ie068e9dc3dd836c83d90e282b10d5202e7a4ba9b
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-on: http://review.coreboot.org/2005
Tested-by: build bot (Jenkins)
Fix debug printks which were not using CONFIG_DEBUG_SPI_FLASH,
which would cause long delays durring boot when SPI devices
were written.
Change-Id: I99fc3d5f847fdf4bb98e2a0342ea418ab7d5fc54
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-on: http://review.coreboot.org/1965
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Mostly preventing inb/outb being used on non-x86
Change-Id: I0434df4ce477c262337672867dc6ce398ff95279
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/2002
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
ARM does not need them, and they're causing trouble
Change-Id: I6c70a52c68fdcdbf211217d30c96e1c2877c7f90
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/2009
Tested-by: build bot (Jenkins)
... on all other systems it will fail terribly ;-)
Change-Id: I7f8d10b71b2dbc798b28aee7c36872685c793fd8
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/2001
Tested-by: build bot (Jenkins)
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Because they use outb instructions, they are bound to fail
on non-PC80 systems like ARM.
Change-Id: I679ac6c0964c06c369cc90556529bb6f629d56f9
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/1974
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Tested-by: build bot (Jenkins)
Instead of adding regparm(0) to each assembler function called
by coreboot, add an asmlinkage macro (like the Linux kernel does)
that can be different per architecture (and that is empty on ARM
right now)
Change-Id: I7ad10c463f6c552f1201f77ae24ed354ac48e2d9
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/1973
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
The ARM architecture is really many architectures, and most
of them need their own toolchain. After discussing with Ron
and David, we decided that we're going to call the architecture
of our ARM board armv7.. This patch cleans out the remainders
of ARCH_ARM in the tree and moves on to consistent ARMv7 naming.
As of now, we only support little endian ARMv7 CPUs. We can
fix that for big endian if/when it comes our way.
Change-Id: Id70c7ef615f600e4d09961d811e7ac974fce4811
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/1968
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
get_option() is used to get a config option (debug loglevel) from
CMOS. However, not all machines have CMOS, so define a dummy inline
function that will return an error code so the caller (console_init())
will use the default loglevel.
Change-Id: I6adf371d79164178f40a83f7608289a6a7673357
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/1962
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Aladyshev Konstantin