Commit Graph

37810 Commits

Author SHA1 Message Date
Duncan Laurie f78ade3e31 mb/google/volteer/variants: Describe USB ports in devicetree
Add the USB ports to the devicetree for describing them in ACPI,
including defining the port relationships and defining the reset
GPIO for the bluetooth device.

BUG=b:151731851
TEST=tested on volteer, all other boards were checked against the
latest available schematic.

Signed-off-by: Duncan Laurie <dlaurie@google.com>
Change-Id: Ia1e5b71e7750a478ff79372c48616bbf5c21b79c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46853
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-11-02 16:53:01 +00:00
Subrata Banik 4ed9f9a507 soc/intel: Use of common reset code block
This patch removes all redundant reset code block from each SoC
and make use of common reset code block(fsp_reset.c) based on
SOC_INTEL_COMMON_FSP_RESET.

Respective SoC Kconfig to choose correct FSP global reset type as
per FSP integration guide.

Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Change-Id: I71531f4cf7a40efa9ec55c48c2cb4fb6ea90531f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45337
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-11-02 10:43:53 +00:00
Subrata Banik 2b2ade9638 soc/intel/common: Create common Intel FSP reset code block
Create SOC_INTEL_COMMON_FSP_RESET Kconfig to have IA common code block
to handle platform reset request raised by FSP. The FSP will use the
FSP EAS v2.0 section 12.2.2 (OEM Status Code) to indicate that a reset
is required.

Make FSP_STATUS_GLOBAL_RESET depends on SOC_INTEL_COMMON_FSP_RESET.

Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Change-Id: I934b41affed7bb146f53ff6a4654fdbc6626101b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47017
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-11-02 10:43:40 +00:00
Angel Pons 22d4397913 azalia: Use `HDA_GCTL_CRST` macro as unset-mask
The `HDA_GCTL_CRST` corresponds to bit zero, so this is equivalent.

Change-Id: I5f4455aa1255f8954ac8b5f1ea5cf8f0874f77a4
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46728
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-02 10:41:35 +00:00
Angel Pons 554713ee0a azalia: Treat all negative return values as errors
Instead of checking whether the return value equals -1, just check if it
is negative. Some Azalia implementations already do it, but most do not.

Change-Id: I43ce72a01c07eff62d645db28c09584b386532ff
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46727
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-02 10:41:15 +00:00
Angel Pons 90cdf705aa sb/intel/lynxpoint: Align with Broadwell
Tested with BUILD_TIMELESS=1, Google Wolf does not change.

Change-Id: Iaed0ba1c14e3f6fac1c9d71f1d4334efc4f0f4e2
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46726
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-02 10:40:50 +00:00
Angel Pons 4fe4661d4e sb/intel/lynxpoint/lpc.c: Simplify PM init sequence
This sequence used to be an array of reg-and-or triplets, but can be
simplified. The resulting sequence is closer to what Broadwell does.

Change-Id: I21e79cbc1e995707b87c40187ddf03b872d02058
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46725
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-02 10:39:48 +00:00
Usha P 412679d892 util/ifdtool: Enable CPU read of the ME region
We are implementing a mechanism in coreboot to update CSME firmware,
this requires coreboot to be able to read CSME region. Exposing the
CSME data is not an issue since the data stored by CSE is all encrypted.

This patch provides a command line option "-r" which will enable read
access to CSME region when locking.

Without this change, locking SPI regions using ifdtool will block BIOS
access to read/access CSME. This will cause failure since BIOS can't
read basic information such as CSME version.

TEST=Flashrom returns success while erasing the SI_ME region.
After rebooting the DUT, DUT boots into OS without any issues on
Drawlat EVT.

Signed-off-by: Usha P <usha.p@intel.com>
Change-Id: I1d9a8e17fba19b717453476fbcb7bcf95b278abe
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46441
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-11-02 10:39:27 +00:00
Duncan Laurie 5abf040265 mb/google/volteer: Add DB_USB3_NO_C option for DB_USB field
Define option value 6 for DB_USB where there is a Type-A port but
no Type-C port on the daughterboard.

BUG=b:151731851
TEST=build volteer boards

Change-Id: I489d24316556dedfecd821e502f1461010b1400f
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46906
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-11-02 10:36:59 +00:00
Felix Singer 3d9fa08bf1 device: Rework bus master option
As an intermediate step for CB:45150, add an additional Kconfig option
which is used to configure bus mastering for any devices and use
PCI_ALLOW_BUS_MASTER to allow coreboot setting the bus mastering bit in
general.

Change-Id: I33b37a79022007a16e97350db61575b63fa8256b
Signed-off-by: Felix Singer <felix.singer@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45149
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-02 06:30:32 +00:00
Sunway d7511f8054 mb/google/kukui: Enable MT8183_DRAM_EMCP for kakadu
The Kakadu project will be using eMCP board design.

BUG=b:171841122
TEST=Boots on chromebook Kakadu successfully.

Signed-off-by: Sunway <lisunwei@huaqin.corp-partner.google.com>
Change-Id: I44668ce630758e49fbf2c6028f56c01f83ff08f8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46871
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Tao Xia <xiatao5@huaqin.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-02 06:29:18 +00:00
Duncan Laurie 78a0160bed soc/intel/denverton_ns: Add PCH_DEVFN_PMC for finding PMC device
In order to support the common PMC functions this device needs to
be able to be located with the common lookup macro.

BUG=b:160996445
TEST=build intel/harcuvar board

Change-Id: If04a82582c07c15bf841d0baa84e31561d211502
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46642
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-02 06:28:50 +00:00
Eric Lai aec4d81e65 mb/google/octopus/var/fleex: Add variant.c into smm stage
variant_smi_sleep is called in smm stage so we need to add
variant.c into smm stage. Otherwise it will call the dummy one.

BUG=b:168075958
BRANCH=octopus
TEST=build image passed.

Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I41df1a30b119ab3e04f9ae01955b6044f137527f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46847
Reviewed-by: Ivy Jian <ivy_jian@compal.corp-partner.google.com>
Reviewed-by: Marco Chen <marcochen@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-02 06:28:38 +00:00
Jes Klinke fbb568347d mb/google/volteer: New variant for Volteer reworked with Dauntless
For development of the firmware to run on the Dauntless TPM, a number of
Volteer2 devices are being reworked to replace the H1 chip with probe
wires to connect to an external Dauntless development board.

Some modification to the AP firmware is required, not least because the
Dauntless chip is connected via I2C bus, instead of SPI.  Most of the
Dauntless developers will not otherwise have a Chrome OS chroot.
Because of the above, I think it makes sense to have a new variant, for
the reworked devices, which I intend to create with this CL.

BUG=b:169526865
TEST=abuild -t GOOGLE_VOLTEER2_TI50 -c max -x

Change-Id: Ibdcd6c2ce3941c229518f21f0e479890b5d76dd1
Signed-off-by: Jes Bodi Klinke <jbk@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46437
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-11-02 06:28:00 +00:00
Patrick Rudolph 49da0cfe46 cpu/intel/car/non-evict/cache_as_ram.S: Add support for longmode
* Use heap for linker script calculated constant to fix relocation
  symbols in mixed assembly code.

Tested on HPZ220:
* Still boots in x86_32.

Tested on Lenovo T410:
* Doesn't need the MMX register fix in long mode.

Change-Id: I3e72a0bebf728fb678308006ea3a3aeb92910a84
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44673
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-11-02 06:26:43 +00:00
Tim Chen f9bc5baee5 mb/google/dedede/var/metaknight: Generate SPD ID for supported parts
Add supported memory parts in the mem_parts_used.txt and generate the
SPD ID for the parts. The memory part being added is:
MT53E512M32D2NP-046 WT:E
K4U6E3S4AA-MGCR
H9HCNNNBKMMLXR-NEE
MT53E1G32D2NP-046 WT:A
K4UBE3D4AA-MGCR

BUG=b:169813211
TEST=Build the metaknight board.

Signed-off-by: Tim Chen <tim-chen@quanta.corp-partner.google.com>
Change-Id: I0d0d22f4790f66b5265803e4dcf01234a16b1993
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46810
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2020-11-02 06:26:08 +00:00
Ronak Kanabar 8586b4020d soc/intel/jasperlake: Set the GpioOverride configuration
Set "GpioOverride" config to override FSP gpio
configuration. FSP will not configure any GPIOs
and rely on GPIO settings programmed before moved to FSP.

BUG=b:150666058
TEST=Build and boot JSLRVP

Cq-Depend: TBD
Change-Id: Ia4036cf0be3a6036d70920743958dc327a652077
Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45901
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-02 06:25:53 +00:00
David Wu 77a23d10bf mb/google/volteer/var/terrador: Enable SaGv support
Enable SaGv for terrador.

BUG=b:171763116
BRANCH=volteer
TEST="emerge-volteer coreboot" compiles successfully.

Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: Ie00166a619424a67f70f870e55822ae2cc6d023d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46841
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Derek Huang <derek.huang@intel.corp-partner.google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
2020-11-02 06:25:31 +00:00
Nico Huber bc2c12c728 libpayload/x86: Try to discover invariant TSC rate
We can skip the PIT-based TSC calibration if we can derive the invariant
TSC rate from CPUID/MSR data. This is necessary if the PIT is disabled,
which is the default, for instance, on Coffee Lake CPUs.

This implementation should cover all Intel Core i processors at least.
For older processors, we fall back to the PIT calibration.

Change-Id: Ic6607ee2a8b41c2be9dc1bb4f1e23e652bb33889
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34170
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2020-11-02 06:24:33 +00:00
Nico Huber 5c9d82bd73 libpayload/x86: Add enumeration of Intel family 6 models
The list is incomplete and only contains what we need in the follow-up
commit. It can be extended at will.

Change-Id: Ibf8ddaf510eb513ee74af3e78da46b04802a91b9
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47059
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-11-02 06:24:10 +00:00
Tim Crawford d0d445564c mb/system76/lemp9: Enable battery charging thresholds
Change-Id: I5131cf350d5b8c2a45f8d8245c0df26742c0d732
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45533
Reviewed-by: Jeremy Soller <jeremy@system76.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-02 06:23:50 +00:00
Tim Crawford a4e75ab0cd ec/system76/ec: Add battery charging thresholds
System76 EC firmware supports setting charging thresholds for a single
battery.

Change-Id: I3d656291c096f320d469274677e9fe6c74819d25
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45532
Reviewed-by: Jeremy Soller <jeremy@system76.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-02 06:23:36 +00:00
Elyes HAOUAS f8051e7c8b ec/system76/ec: Convert to ASL 2.0 syntax
Change-Id: I83a4a3ad8a9fcb6071e0c700bf2be1676847aa9e
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46107
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jeremy Soller <jeremy@system76.com>
2020-11-02 06:23:13 +00:00
Michael Niewöhner d5fc04bdc9 include/acpi: add defines for CPPC versions 1-3
Change-Id: I6abbf98398057b9774fcfd9046ba933b5286e4cd
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46986
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-11-02 06:22:56 +00:00
Frank Chu 5b10ec4361 mb/google/volteer/variants/delbin: Update DPTF parameters for delbin
Configure board specific DPTF parameters for delbin

BUG=b:168958222
BRANCH=volteer
TEST=build and verify by thermal team

Signed-off-by: Frank Chu <frank_chu@pegatron.corp-partner.google.com>
Change-Id: I69aa6046fdc90a2cf59ea3a13fdb15c8bc0d29a2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46676
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-02 06:22:05 +00:00
David Wu 397b46c172 volteer: Create voema variant
Create the voema variant of the volteer reference board by copying
the template files to a new directory named for the variant.

(Auto-Generated by create_coreboot_variant.sh version 4.2.0).

BUG=b:171755775
BRANCH=None
TEST=util/abuild/abuild -p none -t google/volteer -x -a
make sure the build includes GOOGLE_VOEMA

Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: I4e1872d1ebff6fefdfb232f1ff82fce95a1ec643
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47007
Reviewed-by: YH Lin <yueherngl@google.com>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-02 06:21:51 +00:00
Kenneth Chan 914a568ec4 mb/google/octopus/variants/dood: Add G2Touch touchscreen support
Add G2Touch touchscreen support for dood.

BUG=b:171526389
BRANCH=octopus
TEST=emerge-octopus coreboot chromeos-bootimage, and check touchscreen
work.

Signed-off-by: Kenneth Chan <kenneth.chan@quanta.corp-partner.google.com>
Change-Id: Ica7d893de285c2dd1efcd43ac74919bdd5d5ac17
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46675
Reviewed-by: Marco Chen <marcochen@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-02 06:21:07 +00:00
Arthur Heymans f3d65e4998 cpu/x86/smm: Pass smm.ld through src-to-obj
This allows for ccopts symbols and preprocessor to be used inside the
smm.ld linker script.

Change-Id: I4262c09ca52c1fca43c1c115530efe489a722c32
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44321
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-02 06:20:53 +00:00
Eric Lai a9a48b6839 mb/google/zork/var/vilboz: Update touch screen power sequence
Add ELAN touch support and update Goodix settings.

BUG=b:157265632
BRANCH=zork
TEST=emerge coreboot and check both touch screen are workable.

Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: Icfc2421061e8b3163d7d5108673351bc17df20ec
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46929
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Martin Roth <martinroth@google.com>
2020-11-02 06:18:12 +00:00
Arthur Heymans fe9d2119a6 soc/intel/fsp-car: Use the coreboot defined stack
The stack needs to be in the coreboot defined region to not collide
with other symbols.

Change-Id: I02a379d2ac73ae30239bd45859c3f09de1a9d0e0
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37278
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2020-11-02 06:17:41 +00:00
Arthur Heymans 087fe9fe27 soc/intel/xeon_sp/bootblock.c: Report the FSP-T output
Change-Id: I03841f8263203ee306f83b8f8e859ec03edc3bd3
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46885
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-02 06:16:53 +00:00
Arthur Heymans 5a66334911 drivers/intel/fsp2_0: Add function to report FSP-T output
This allows to compare the FSP-T output in %ecx and %edx to coreboot's
CAR symbols:

Change-Id: I8d79f97f8c12c63ce215935353717855442a8290
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46884
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-11-02 06:16:37 +00:00
Furquan Shaikh d7388d13f7 soc/intel/common/cse: Add dependency on SOC_INTEL_CSE_LITE_SKU
This change adds the dependency on SOC_INTEL_CSE_LITE_SKU for the
following configs:
1. SOC_INTEL_CSE_FMAP_NAME
2. SOC_INTEL_CSE_RW_CBFS_NAME
3. SOC_INTEL_CSE_RW_FILE

These configs aren't really useful for platforms not using CSE Lite
SKU.

Change-Id: Id48ab36b7e75301d50122916d153f494d755ae77
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46905
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-02 06:16:23 +00:00
Furquan Shaikh 160fc4736b drivers/wifi/generic: Use is_dev_enabled() instead of dev->enabled
This change replaces the checks for dev->enabled with the helper
function `is_dev_enabled()`.

Change-Id: Iacceda396c9300bbfa124e76fb9c99d86313ea0f
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46904
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-02 06:15:41 +00:00
Furquan Shaikh cbe2fd351c wifi: Drop PCI IDs for JfP and HrP
This change drops the PCI IDs for Jefferson Peak and Harrison Peak
CNVi modules from wifi/generic drivers as well as pci_ids.h. These IDs
actually represent the CNVi WiFi controller PCI IDs and are now
supported by intel/common/block/cnvi driver.

The only ID that is being dropped without adding support in
intel/common/block/cnvi driver is
PCI_DEVICE_ID_HrP_6SERIES_WIFI(0x2720) since this was not found in the
list of PCI IDs for any SoC.

Change-Id: I82857a737b65a6baa94fb3c2588fe723412a7830
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46866
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-02 06:15:27 +00:00
Furquan Shaikh edac4ef6d4 mb, soc/intel: Reorganize CNVi device entries in devicetree
This change reorganizes the CNVi device entries in mainboard
devicetree/overridetree and SoC chipset tree to make it consistent
with how other SoC internal PCI devices are represented i.e. without a
chip driver around the SoC controller itself.

Before:
chip drivers/wifi/generic
	register "wake" = "..."
	device pci xx.y on end
end

After:
device pci xx.y on
	chip drivers/wifi/generic
		register "wake" = "..."
		device generic 0 on end
	end
end

Change-Id: I22660047a3afd5994400341de0ca461bbc0634e2
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46865
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2020-11-02 06:15:06 +00:00
Furquan Shaikh 23e88135bb soc/intel: Add a driver for CNVi WiFi/BT controllers
This change adds a common block driver for CNVi WiFi/BT controllers in
Intel SoCs. This driver uses the common PCI dev operations in addition
to generating ACPI device node and returning ACPI name for the
controller device.

This change also selects this driver for CML, GLK, ICL, JSL and TGL.

Change-Id: I69a832be918d4b9f4fbe3a40913d4542a457a77c
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46864
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2020-11-02 06:14:38 +00:00
Furquan Shaikh 9e1fab0076 pci_ids: Add PCI IDs for CNVi WiFi/BT controllers
This change adds PCI IDs for CNVi WiFi/BT controllers for CML, GLK,
ICL, JSL and TGL.

Change-Id: Id45f65d0ef5a7782c08ddd70eb22b26072c8ef4b
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46863
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2020-11-02 06:14:24 +00:00
Furquan Shaikh d4367505f1 drivers/wifi/generic: Add support for CNVi dummy device ops
This change reorganizes drivers/wifi/generic to add a new
device_operations structure for dummy CNVi device. This is done to
make the organization of CNVi PCI device in devicetree consistent
with all the other internal PCI devices of the SoC i.e. without a chip
around the PCI device.

Thus, with this change, CNVi entry in devicetree can be changed from:
```
chip drivers/wifi/generic
	register "wake" = "xxyyzz"
	device pci xx.y on end # CNVi PCI device
end
```

to:

```
device pci xx.y on
	chip drivers/wifi/generic
		register "wake" = "xxyyzz"
		device generic 0 on end # Dummy CNVi device
	end
end # CNVi PCI device
```

The helper functions for ACPI/SMBIOS generation are also accordingly
updated to include _pcie_ and _cnvi_ in the function name.

Change-Id: Ib3cb9ed9b81ff8d6ac85a9aaf57b641caaa2f907
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46862
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-02 06:14:12 +00:00
Furquan Shaikh 6017abbc2c drivers/wifi/generic: Split wifi_generic_fill_ssdt into two functions
This change splits `wifi_generic_fill_ssdt()` into following two
functions:
1. `wifi_ssdt_write_device()`: This function writes the device, its
address, _UID and _DDN.

2. `wifi_ssdt_write_properties()`: This function writes the properties
for WiFi device like _PRW, regulatory domain and SAR.

This split is done so that the device write can be skipped for
CNVi devices in follow-up CLs. It will allow the SoC controller
representation for CNVi PCI device to be consistent with other
internal PCI devices in the device tree i.e. not requiring a
chip driver for the PCI device.

Because of this change, _PRW and SAR will be seen in a separate
block in SSDT disassembly, but it does not result in any functional
change.

Observed difference:
Before:
Scope (\_SB.PCI0.PBR1)
{
	Device (WF00)
	{
		Name (_UID, 0xAA6343DC)
		Name (_DDN, "WIFI Device")
		Name (_ADR, 0x0000000000000000)

		Name (_PRW, Package() { 0x08, 0x03 })
	}
}

After:
Device (\_SB.PCI0.PBR1.WF00)
{
	Name (_UID, 0xAA6343DC)
	Name (_DDN, "WIFI Device")
	Name (_ADR, 0x0000000000000000)
}

Scope (\_SB.PCI0.PBR1.WF00)
{
	Name (_PRW, Package() { 0x08, 0x03 })
}

Change-Id: I8ab5e4684492ea3b1cf749e5b9e2008e7ec8fa28
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46861
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2020-11-02 06:13:54 +00:00
Furquan Shaikh 2736c82956 drivers/wifi/generic: Move ACPI functions to a separate file
This change reorganizes the WiFi generic driver to move the ACPI
functions to a separate file. This change is done to reduce the noise
in generic.c file and improve readability of the file.

Change-Id: If5fafb5452fb5bad327be730fcfc43d8a5d3b8ec
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46860
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2020-11-02 06:13:10 +00:00
Furquan Shaikh 507a98b689 drivers/wifi/generic: Move SMBIOS functions to a separate file
This change reorganizes the WiFi generic driver to move the SMBIOS
functions to a separate file. This change is done to reduce the noise
in generic.c file and improve readability of the file.

Change-Id: I38ed46f5ae1594945d2078b00e8315d9234f36d7
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46859
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2020-11-02 06:12:57 +00:00
Furquan Shaikh 2b5be8857b drivers/wifi/generic: Use acpigen_write_ADR_pci_device
This change uses the helper function `acpigen_write_ADR_pci_device()`
to write _ADR object for the WiFi device.

Change-Id: I3ba38f3ec4d8024209840e93bebf2d39bbef7685
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46858
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2020-11-02 06:12:42 +00:00
Martin Roth 89815c96a6 soc/amd/picasso: Put transfer buffer into common ld file
Instead of having the same linker layout for the transfer buffer between
the x86 & PSP linker layout scripts, put the common layout into a file
shared between the other linker scripts.

BUG=None
TEST=Boot zork board, verify the buffers are aligned.
BRANCH=Zork

Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: Ib9d9d8b046bc9e9e7a4ee939324960bfc44c3508
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46900
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2020-11-02 06:12:11 +00:00
David Wu 0d76194a1b mb/google/volteer: Disable DPTF active policy for terrador and todor
Terrador and Todor are fanless design, so disable DPTF active policy.

BUG=b:171019363,b:170699797
BRANCH=volteer
TEST=build and verify by thermal team

Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: I53a33b8706d7a7d4013a2a5627a620223fcffc3e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46874
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-02 06:11:21 +00:00
Iru Cai a568d605e9 ec/hp/kbc1126: Support using a different GPE
HP EliteBook Folio 9480m uses the HP KBC1126 EC ACPI interface, but
with a different GPE, so add a Kconfig option to support using a
different GPE.

Change-Id: I3b78567e1387c96bf173e4370aa3c836bbddac0b
Signed-off-by: Iru Cai <mytbk920423@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45576
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-02 06:08:54 +00:00
Srinidhi N Kaushik b57f22fc5b vendorcode/intel/fsp: Update Tiger Lake FSP Headers for FSP v3425
Update FSP headers for Tiger Lake platform generated based on FSP
version 3425. Previous version was 3373.

BUG=b:172045149
BRANCH=none
TEST=build and boot delbin

Cq-Depend:chrome-internal:3373431
Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Change-Id: I58d165d452c8c6ae2eec92524109a568f7e581a9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47041
Reviewed-by: Dossym Nurmukhanov <dossym@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-02 04:43:39 +00:00
Matt DeVillier 184c794086 docs/librem_mini: update CPU, known issues section
Both 8565U and 8665U CPUs are used in the Librem Mini.

SATA issue updated based on addition of HSIO PHY tuning params
and resulting changes.

Change-Id: I33a093ccfea077402e1b3651f9ca5d6d8a2818f8
Signed-off-by: Matt DeVillier <matt.devillier@puri.sm>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46983
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2020-10-31 21:46:06 +00:00
Patrick Georgi 8aa087ece6 .gitignore: Ignore .test/.dependencies globally
These were originally ignored only inside util/ but these files
shouldn't be tracked anywhere.

Change-Id: Ie0846bd8bdd6e52f420f9dd2e72a8a922102ff90
Signed-off-by: Patrick Georgi <patrick@georgi.software>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47012
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-10-31 18:21:36 +00:00
Martin Roth 09e032e59f Makefile: Remove possibly illegal characters from doxyplatform
The CONFIG_MAINBOARD_PART_NUMBER string can have characters in it that
don't work in the doxyplatform make script under sh, so change any
non-alphanumeric characters to an underscore.

Also strip all the quotes - they aren't needed.

The spaces in the "QEMU x86 i440fx/piix4" platform are one example of
this.

Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: I10bc6a8a245a34e89c859ff46835bde35aaa4286
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46287
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2020-10-31 18:21:06 +00:00