In order to support using the common ACPI code on more platforms
than just Apollo Lake the DPTF code needs to be told what the
PCI address is for the CPU thermal device.
Change-Id: I638f2387330bbc42f64eb0fb676ee32c5df6572e
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/29757
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Extended events will be handled by the OS kernel driver, but that
driver needs a method exposed by ACPI to read the event data from
the EC and into a buffer.
Tested by generating a hotkey event and reading the buffer from
the Linux kernel driver with acpi_evaluate_object().
Change-Id: Ic8510e38d777a5dd31a5237867313efefeb2b48e
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/29674
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add EC command to enable WiFi radio and send that command at
startup. Tested to ensure WiFi is functional on a sarien board.
Change-Id: Iac46895c7118567e1eb55ea33051a1662103b563
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/29673
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Enable the COM1 ACPI device based on the existing Kconfig option
CONFIG_DRIVERS_UART_8250IO instead of expecting the mainboard to
also define another value for ACPI.
Change-Id: I69361cc2c245cfcad3e4f57567bf56d5a26f0b06
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/29672
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Set WWAN_GPIO_PERST#(GPP_D22) to low at bootblock stage to meet
the logic output for WWAN_PERST#_R to high.
BUG=120004153
TEST=Boot up Sarien board, check WWAN get detected as USB
devices through lsusb.
Change-Id: I16f1101c64dfd4dcb5e8342fdb925951f6f2f90b
Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/30017
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
The different PLLs in the fu540 use the same register layout, so use one
function (configure_pll) to program a PLL and wait for it to lock. This
also makes it possible to dynamically calculate the PLL settings later.
TEST=Boot until "Payload not loaded" on HiFive Unleashed
Change-Id: I5c0cee886bad5758c70f967d2bb998c1e1a736ab
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/c/29356
Reviewed-by: Philipp Hug <philipp@hug.cx>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* Verify the flash write protection on each boot
* Program non-volatile write protection on first boot
Tested using I715791b8ae5d1db1ef587321ae5c9daa10eb7dbc.
The bootblock is write-protected as long as the #WP pin is asserted low:
* Reprogramming of the status register fails.
* Trying to write to WP_RO region fails.
Programming the WP_RO is only possible if #WP pin is high.
Change-Id: I6a940c69ecb1dfd9704b2101c263570bebc5540e
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/29532
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
The TB has to be inverted to actually protected the correct region.
Tested on elgon using I67eb4ee8e0ad297a8d1984d55102146688c291fc.
Change-Id: I715791b8ae5d1db1ef587321ae5c9daa10eb7dbc
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/30014
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
update the new sku ids of bard/ekko
BUG=b:120257865
BRANCH=Nami
TEST=emerge-nami coreboot chromeos-bootimage
write the new sku id in cbi and verify the fw to
check it can get the correct settings by the sku id
Change-Id: I3579d3d8042a270d8ea8e2f7b5612ff8e2cdfa7b
Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/30031
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This change enables mode change as a wake source from S3 and
S0ix. Thus, any time the device switches between clamshell and tablet
mode while it is suspended, it will be treated as a valid user event
and hence wake source.
BUG=b:120349473
BRANCH=octopus
TEST=Verified that octopus wakes up on mode transitions.
Change-Id: Ib224df434730f873ce5514303e5d043cbc85a9a4
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/30001
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Backlight control of internal panels likely won't work as configuration
for that seems absent in coreboot. Also, libgfxinit doesn't support any
MIPI/DSI connections, yet, and neither Gemini Lake.
TEST=Booted work-in-progress port kontron/mal10 with VGA text and
linear framebuffer modes. DP display came up.
Change-Id: I7b111f1cdac4d18f2fc3089f57aebf3ad1739e5d
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/29903
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Removes a warning in Linux about FACP.
Change-Id: Ia12302a4dcd34eacdcc8ae16bd39e951e616c6ea
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/30011
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
This change adds support to print ME version if UART_DEBUG is
enabled. Check for UART_DEBUG is necessary because talking to ME to
get the firmware version adds ~0.6 seconds to boot time.
TEST=Verified on octopus that ME version printed is correct.
Change-Id: I41217371558da1af694a2705e005429155d62838
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/29989
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Replace IO access to ACPI registers with the new MMIO access functions.
BUG=b:118049037
TEST=Build and boot grunt. Test ACPI related functionality.
Change-Id: I7544169bb21982fcf7b1c07ab7c19c6f5e65ad56
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/c/29296
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
ACPI registers can be accessed through IO or through MMIO. However, the
offset relationship is not one to one. Therefore, definitions with the
correct offset for MMIO access are needed.
BUG=b:118049037
TEST=Use Chrome OS IOTOOLS io_readxx and mem_readxx to find the correct
relationship between ACPI IO and ACPI MMIO.
Change-Id: Id20754c0fc0af35bc9eb1a4b40c62fbf9ed6304d
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/c/29294
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
This makes the mainboard able to boot again.
Change-Id: Id96fbfd5c815431dba2f030fca62a5ea16b97393
Signed-off-by: Kevin Cody-Little <kcodyjr@gmail.com>
Reviewed-on: https://review.coreboot.org/c/29994
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add myself as a maintainer of the four mainboards I ported. For those
which were added as a variant, add myself as a maintainer of the whole
mainboard group.
Change-Id: I0e1b54279027fae82ea9f2825e6f27d38ef3c746
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/29995
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
"if" is preferable over "#if", because it lets the compiler perform
syntax and type checks even if CONFIG_CONSOLE_SERIAL is disabled.
Change-Id: I45a763f2d854fbe9082795bc74de7a9d0fded3c9
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/c/29336
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Hug <philipp@hug.cx>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
clock_get_coreclk_khz() already detects whether the PLL or the input
clock (hfclk) is used.
Tested on HiFive Unleashed.
Change-Id: I264977b0de0b81ef74a014984b6d33638ab33f4b
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/c/29334
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Hug <philipp@hug.cx>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Philipp has been reviewing and writing RISC-V-related code for a while.
Change-Id: I3f2d3a61f66343a6e0350909edfe466d2ee6c089
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/c/29980
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Reviewed-by: Philipp Hug <philipp@hug.cx>
The common finalise code is used by bd82x6x, Lynx Point, and Ibex Peak.
Lynx Point now benefits from being able to write-protect the flash chip.
For Lynx Point, writing the SPI OPMENU now happens in ramstage, as done
in bd82x6x.
Tested on an ASRock H81M-HDS (Lynx Point). When write-protection is
configured, flashrom reports all flash regions as read-only, and does
not manage to alter the contents of the flash chip.
Also tested on an ASUS P8H61-M LX (Cougar Point). Everything seems to
work as before.
Change-Id: I781082b1ed507b00815d1e85aec3e56ae5a4bef2
Signed-off-by: Tristan Corrick <tristan@corrick.kiwi>
Reviewed-on: https://review.coreboot.org/c/29977
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
The finalise handler is not called during S3 resume when using the
`BS_PAYLOAD_BOOT` approach. So, adopt the `lpc_final` approach used by
bd82x6x and others.
Tested on an ASRock H81M-HDS. The finalise handler is now called on
the normal boot path, and during S3 resume.
Change-Id: I9766a8dcbcb38420e937c810d252fef071851e92
Signed-off-by: Tristan Corrick <tristan@corrick.kiwi>
Reviewed-on: https://review.coreboot.org/c/29976
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
The ASRock H81M-HDS doesn't implement a finalise handler. To fix
this, and reduce code duplication in the process, make a common
implementation. There should be no functional change to boards with
existing finalise handlers, since the code is identical among them and
the new, common implementation.
Tested on an ASRock H81M-HDS. The finalise handler works.
Change-Id: I13b581a2219288019a4e0c9e618db3ac7c3c15ab
Signed-off-by: Tristan Corrick <tristan@corrick.kiwi>
Reviewed-on: https://review.coreboot.org/c/29975
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
The WACOM 5C01 touch panel power-up delay of 10mS is too aggressive
and causes "failed to change power setting" errors in the kernel, so
this change increases the power-up delay to 20mS which allows enough
time for the WACOM device's i2c controller to wake up.
BUG=b:120090384
BRANCH=none
TEST=flash and boot nocturne, log into kernel, execute the following
command and make sure the string is not found :
dmesg | grep "failed to change power setting"
Change-Id: I1db0b3f5ce666b79d8ada2939ec865233ce52a56
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/29988
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
We discovered that the gpios previously used for FPMCU_INT_L were in
two different groups with two different voltages (C group was at 3.3V
and D group was at 1.8V). Moving both to B group which is at 3.3V.
BUG=b:119447525
BRANCH=Nami
TEST=unlock OS with fingerprint
register fingerprint
run powerd_dbus_suspend and see if it goes int s0ix
Change-Id: I2332b0eb7a2f74e8178b95a23c8ac2091027a071
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/29872
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Update USB port info according to the schematic file.
BUG=none
BRANCH=master
TEST=Compiles successfully and boot on DUT.
Change-Id: I7383b3d676fd7c775a6d749c70af65b28cf941eb
Signed-off-by: David Wu <David_Wu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/29912
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Now that the relationship between IO access and MMIO access has been
established, create read/write functions to access ACPI standard registers
through MMIO.
BUG=b:118049037
TEST=Build grunt
Change-Id: I32c26f342885c0d99b082be98730edcf16ab5dfc
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/c/29295
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Handle situation when first NIC is not BDF 1:0.0. The PCI enumeration
is different when a external PCIe device is connected to mPCIe2 slot
which is routed to first PCIe bridge. The first NIC is then assigned
BDF 2:0.0, because it is connected to the second PCIe bridge.
Read the secondary bus number from the NIC PCIe bridge before attempting
to read MAC adress and calculating serial number.
Change-Id: I9f89a6f3cd0c23a2d2924e587338f69c260b12f8
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/29842
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
This can be used to select the proper VBT.
Change-Id: Id3f6ba3ae31a5ab47f44d207678c1c4a6a43b7ec
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/29925
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Use of device_t is deprecated.
Change-Id: Ief858f6612d1c7b4b0c286cf5938f8c29055f1b5
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/29915
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Use of device_t is deprecated.
Change-Id: I2c88642133d3cbf33015e3e1e855fb2c786878d6
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/29914
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
All i82801gx targets now use SMM_TSEG.
Change-Id: Ib4e6974088a685290ed1dddf5228a99918744124
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/25599
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
This also caches the TSEG region and therefore increases MTRR usage a
little in some cases.
Change-Id: I5f947cfae730b67bc76a581bc90cb10e5a2a4a52
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/25598
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This also caches the TSEG region and therefore increases MTRR usage
a little in some cases.
Currently SMRR msr's are not set on model_1067x and model_6fx since
this needs the MSRR enable bit and lock set in IA32_FEATURE_CONTROL.
This will be handled properly in the subsequent parallel mp init
patchset.
Tested on Intel DG41WV, resume from S3 still works fine.
Change-Id: I317c5ca34bd38c3d42bf0d4e929b2a225a8a82dc
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/25597
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Use the common SMM_TSEG code to relocate the smihandler to TSEG.
This also caches the TSEG region and therefore increases MTRR usage a
little in some cases.
This fixes S3 resume being broken introduced by CB:25594
"sb/intel/i82801gx: Use common Intel SMM code".
Currently SMRR msr's are not set on model_1067x and model_6fx since
this needs the MSRR enable bit and lock set in IA32_FEATURE_CONTROL.
This will be handled properly in the subsequent parallel mp init
patchset.
Tested on Intel d945gclf and Lenovo Thinkpad X60.
Change-Id: I0e6374746c3df96ce16f1c4a177af12747d6c1a9
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/25595
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Use the common Intel code to set up smm and the smihandler.
This is expected to break S3 resume and other smihandler related
functionality as this code is meant to be used with CONFIG_SMM_TSEG.
The platform (x4x) using this southbridge will adapt
the CONFIG_SMM_TSEG codepath in subsequent patches.
Change-Id: Id3b3b3abbb3920d68d77fd7db996a1dc3c6b85a3
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/25596
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
TEST=on Chromebook Kevin with 64bit userland, it works well.
Change-Id: If16065000214c6cff9c14a14c5b5f44faca38153
Signed-off-by: Adam Kallai <kadam@inf.u-szeged.hu>
Reviewed-on: https://review.coreboot.org/c/29978
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Sync the FSP settings with what coreboot does. Why both FSP and coreboot
configure this redundantly stays a secret.
TEST=Set SERIRQ_CONTINUOUS on kontron/mal10. A CPLD connected to LPC
works correctly now, but was confused by the wrong settings before
because the FSP defaults allowed to disable the LPC clock.
Change-Id: Id1c7180f460678bf0f9458228591050dd628c052
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/29901
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Use acpigen_write_processor_cnot to implement notifications to the CPU.
Change-Id: I01e4397b9a1c15eff4b856cbc697fa2b4bc9761f
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/29893
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Use acpigen_write_processor_cnot to implement notifications to the CPU.
Change-Id: If482c64e7133cc6d82472d121ac138fc1b60a183
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/29892
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: David Guckian
Duncan Laurie