Commit Graph

30258 Commits

Author SHA1 Message Date
Tony Huang 593d1cf817 mb/google/octopus: Add custom SAR values for Blooguard
Google project name is Bloog.
Bloog is 12-inch LCD.
Blooguard is 14-inch LCD so would prefer to use a different SAR values instead.
Use sku-id to load the SAR values.

BUG=b:135078377
BRANCH=octopus
TEST=build and verify SAR load by sku-id

Change-Id: Id80df28a961eb1f62714558df2b219aa552ecb97
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33935
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2019-07-03 02:15:05 +00:00
Julius Werner eda20b677f vboot: Use CONFIG_VBOOT_MIGRATE_WORKING_DATA on all platforms
When we added CONFIG_VBOOT_MIGRATE_WORKING_DATA, the idea was that on
some Arm platforms the original working data buffer was in SRAM, which
stays accessbile for the whole runtime of the system. There is no reason
to migrate it into CBMEM on those platforms because ramstage and the
payload could continue to access it in SRAM.

Now that we've had a couple of months of experience with this option, we
found that most of our Arm platforms have some issue that requires
migrating anyway, because BL31 often claims SRAM for itself and makes it
inaccessible to the payload. On the remaining platforms, accessing SRAM
from the payload is possible but still an issue, because libpayload
doesn't have enough memory layout information to set up proper page
tables for it, so we're accessing it uncached and at risk of alignment
errors.

Rather than having to figure out how to map the right SRAM range for
every platform in the payload, let's just get rid of the option.
memcpy()ing 12KB isn't worth this much hassle.

Change-Id: I1b94e01c998f723c8950be4d12cc8f02b363a1bf
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33952
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Joel Kitching <kitching@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2019-07-03 00:38:41 +00:00
Akash Asthana 275f7ba5ac sdm845: Update macro definition in CB clock driver
Use literals KHz & MHz for kilohertz and megahertz frequency usages
in macro definition.

Change-Id: If1ca6e5e7b0603f93f3c980cc85af470fdcd54ba
Signed-off-by: Akash Asthana <akashast@codeaurora.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33811
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2019-07-02 21:56:46 +00:00
Marshall Dawson d19fa78ae7 arch/x86: Fix spelling error in BERT comment
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Change-Id: I57c0bcfbe0d96aac106f771e8efb3bd471302c25
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33965
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-02 18:50:10 +00:00
Patrick Georgi 848e30daa1 cbfstool: show "preserved" flag in cbfstool layout output
The flag is useful for updaters to determine which areas to leave
alone, such as VPD (vital product data) regions that are set in
factory and might contain unique (MAC addresses) or hard to obtain
(calibration output) data.

It's also useful to see which regions are marked as such.

Change-Id: Ic0a229d474b32ac156cfabc917714ce9d339bac6
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33604
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
2019-07-02 18:48:02 +00:00
Marshall Dawson 914e6b44bb cpu/amd/msr: Clarify MMIO_CONF shift value
MMIO_BUS_RANGE_SHIFT is a numerical value and not a bit field.
Change it to simply 2.  Otherwise its usage winds up evaluating
to BusRange << (1 << 1).

Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Change-Id: I2a6ecfc9fbfd45f69194b8daef43ff84a1dfd5fc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33942
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2019-07-02 18:38:56 +00:00
Keith Short bf2c693f89 libpayload/usb: Increase USB request timeout to 5 s
Increase the timeout for USB requests to 5 seconds for all USB host
controllers.

Prior to this fix, the xCHI driver was detecting false timeouts during
SET ADDRESS requests when nested downstream hubs were connected to the
xHCI root hub.

BUG=b:124730179
BRANCH=sarien
TEST=Build libpayload and depthcharge on sarien/arcada.
TEST=Without change replicate USB set address timeouts in depthcharge
when dock and 4K monitor connected (which includes a total of 4 USB
hubs).  With timeout fix, depthcharge boots OS with no USB errors and
the same USB topology.  Note that this tests xHCI operation only.

Change-Id: I53e3e67d893420e7c9e8b52c47dd0edb979e5468
Signed-off-by: Keith Short <keithshort@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33671
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-07-02 17:42:18 +00:00
Arthur Heymans 9d0b7b9021 arch/riscv: Make RISCV specific options depend on ARCH_RISCV
Also don't define the default as this results in spurious lines in the
.config.

The only difference in the generated config.h is that for most board
ARCH_RISCV_M goes from 1 to 0. This should not matter.

Change-Id: I3e8c1cc5696d621e243696a3b5e34f62ab69a688
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31311
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-02 16:16:31 +00:00
Elyes HAOUAS 4d4a13f797 drivers/pc80/rtc/mc146818rtc_boot: Use size_t for length
Change-Id: I877e19c014759e33b9cc48ff9ee27e898737aece
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33805
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-07-02 16:15:14 +00:00
Elyes HAOUAS 63f98f2304 src: Use CRx_TYPE type for CRx
Change-Id: If50d9218119d5446d0ce98b8a9297b23bae65c72
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33816
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-02 16:14:36 +00:00
Paul Fagerburg 7803e487bd soc/intel/cannonlake: Add support to log XHCI wake events
Enhance elog wake source information with more details about which USB port
resulted in a wake from S3 or S0ix.

BUG=b:123429132
BRANCH=none
TEST=``FW_NAME=hatch emerge-hatch chromeos-ec depthcharge vboot_reference
libpayload coreboot-private-files intel-cmlfsp coreboot-private-files-hatch
coreboot chromeos-bootimage``
Ensure /build/hatch/firmware/image-hatch.serial.bin has been built.

Plug a keyboard into a USB port on the DUT.
Switch the DUT to the console (Ctrl-Alt-F2, or use the AP console via
servo).
On the console, run ``powerd_dbus_suspend``.
Wait for the DUT to enter low power mode.
Verify low power mode by issuing the ``powerinfo`` command on the EC
console (via servo). Expect to see ``power state 4 = S0ix``.
Press a key on the USB keyboard.
The DUT wakes up.
On the console, run ``mosys eventlog list`` and look for the wake source.

156 | 2019-06-26 09:46:07 | S0ix Enter
157 | 2019-06-26 12:14:05 | S0ix Exit
158 | 2019-06-26 12:14:05 | Wake Source | Internal PME | 0
159 | 2019-06-26 12:14:05 | Wake Source | GPE # | 109

Program image-hatch.serial.bin into the DUT using flashrom.
Repeat the ``powerd_dbus_suspend``, ``powerinfo``, ``mosys eventlog list``
sequence.

12 | 2019-06-26 14:52:23 | S0ix Enter
13 | 2019-06-26 14:53:07 | S0ix Exit
14 | 2019-06-26 14:53:07 | Wake Source | PME - XHCI (USB 2.0 port) | 3
15 | 2019-06-26 14:53:07 | Wake Source | GPE # | 109

Change-Id: Ie9ef870e219733dea9806c766f5351db25689b32
Signed-off-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33843
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2019-07-02 16:14:02 +00:00
Jacob Garber 0476332161 util/cbmem: Enable -Wmissing-prototypes
Change-Id: Ia8482dc9b6ad800826152c2d3e9813190b0b574e
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33853
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
2019-07-02 16:12:21 +00:00
Jacob Garber 79a2f4767d util/cbmem: Make internal functions static
These functions are only used in cbmem, so they can be made static.

Change-Id: I21f7d7c21064a8ae951e6d96b28c2ddcf52c0006
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33852
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
2019-07-02 16:12:09 +00:00
Jacob Garber 4d543b5aa6 util/cbmem: Enable -Wextra
This enables extra useful warnings.

Change-Id: I4afbbb0fefb32a7d954aafd87df17075b0abe6f7
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33851
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
2019-07-02 16:11:57 +00:00
Jacob Garber 414d5d8698 util/cbmem: Use correct integer types for loop indices
Make sure that the type of the loop index matches the type of the upper
bound. This fixes several -Wsign-compare warnings.

Change-Id: Iaa94ce93bc35d523bc782ad914bfd283606becac
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33850
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
2019-07-02 16:11:46 +00:00
Bora Guvendik a88921e2b0 3rdparty/fsp: Update submodule pointer
Update fsp submodule pointer to Coffee Lake FSP 7.0.64.40

github commit:
59964173e1

Change-Id: I864404a03be63aa60e81db21af16d69cda2d4e12
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33642
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-02 16:11:03 +00:00
Elyes HAOUAS 1c9bd9ce61 arch/x86: Fix cpu_cpuid_extended_level() return type
`cpuid_eax()` returns an unsigned integer.

Change-Id: Iebb6501130bc9ae333d45ae9d2e10c918245a6d1
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33814
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-07-02 16:10:03 +00:00
Patrick Georgi 328d2e2a7d util/docker/coreboot.org-status: Add more "nice" names for CPUs
It's not perfect and we'll need to find a better place for that,
but I'll look into that as part of the big board-status rework.

Change-Id: I2ae50c58e3796563e0b2370105abc82b7e2e042a
Signed-off-by: Patrick Georgi <patrick@georgi.software>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33930
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
2019-07-02 16:08:18 +00:00
Patrick Georgi 3b34ef29b3 util/release: add more categories
Change-Id: I73cd50da7b2f1aaf1ab05daad4997c5e48172f25
Signed-off-by: Patrick Georgi <patrick@georgi.software>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33929
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
2019-07-02 16:08:05 +00:00
Shelley Chen 328b77a5e9 mb/google/hatch: Set trackpad irq and wake to GPP_A21
Previously, We had to use GPP_A21 for trackpad wake and GPP_D21 for
trackpad interrupts due to ITSS not honoring the INVERT config.  Now
that's fixed, we can configure trackpad wake and interrupts on GPP_A21
only.

BUG=b:130436471
BRANCH=None
TEST=1. boot a hatch device and make sure we can move the cursor with the trackpad
     2. Run powerd_dbus_suspend and wake by clicking on the trackpad and ensure
        through "mosys eventlog list" that the wake source is the trackpad.\
     3. Run "echo mem > /sys/power/state", wait until device goes into S3,
        click trackpad to ensure device wakes.

Change-Id: I26a99206c42ba442f91ae577b98366fc2fd6c0ca
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33820
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
2019-07-02 15:57:59 +00:00
Shelley Chen ad23778d23 mb/google/hatch: Add INVERT to all IOAPIC pads
Now that ITSS config is fixed, we can set the IOAPIC pad configs
correctly.

BUG=b:123967687
BRANCH=None
TEST=Make sure Hatch is booting and tested out trackpad to make
     sure can move cursor and wake by clicking on the trackpad
     after running powerd_dbus_suspend.

Change-Id: I0b125996338b6f16e03b7ca184f6337c696a5f64
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33819
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-02 15:57:13 +00:00
Marshall Dawson c645ae069b soc/amd: Add picasso to Kconfig
Change-Id: I7031b07ae105a14be3c5d4e52ecc1364956fd845
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33750
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-02 14:33:42 +00:00
Martin Roth 778c8a77c1 soc/amd/picasso: Stub out bootblock
Remove all Picasso bootblock support.  CAR is not a supportable
feature, and the first code executed at the reset vector will be
a hybrid romstage.  Details for this implementation may be found
in Documentation/soc/amd/picasso/family17h.md.

TEST=None
BUG=b:130804851

Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: I8edf45c02dc5bfcdca03abf1294db4be508682cf
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32413
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2019-07-02 14:32:41 +00:00
Martin Roth d7e3ead835 soc/amd/picasso: Update stoney paths to picasso
Update paths.  There are still a few paths in Kconfig relating to PSP
and the firmware directory table.  Those will be updated in a follow-on
commit.

TEST=None
BUG=b:130804851

Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: I18f3d80dbeabd754ebcee6593864fd613fc2ef7b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32412
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-02 14:32:18 +00:00
Martin Roth 070e79ea92 soc/amd/picasso: Rename makefile.inc back to Makefile.inc
Now that the Makefile is updated, we can change the name back without
it affecting the Stoney build.

TEST=None
BUG=b:130804851

Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: I18ee48865fb64265f38179560265827783d50820
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32411
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2019-07-02 14:32:00 +00:00
Martin Roth 1f33762d77 soc/amd/picasso: Change SOC_AMD_STONEY* to SOC_AMD_PICASSO
TEST=None
BUG=b:130804851

Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: Ie466bc39ed6aa9d2a8651bd9290090b83cd97d74
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32410
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-02 14:15:18 +00:00
Martin Roth 5f672636d6 soc/amd/picasso: Change header guards from stoney to picasso
TEST=None
BUG=b:130804851

Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: I32b7dbeae7538884311ccfc3a0e8db63c48fe356
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32409
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2019-07-02 14:12:06 +00:00
Martin Roth 360035ee5b soc/amd/picasso: Remove ST files not used for PCO
Remove files that aren't needed for the picasso port.

Remove traces of AGESA v5 (includes binaryPI support files).  Remove
SPD helper.

Picasso (and all AMD Family 17h processors) have a very different
boot flow from previous products.  Memory is initialized by the PSP
before the x86 processor is released from reset.  The SPD is read by
the PSP, so it's not needed in coreboot.

TEST=None
BUG=b:130804851

Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: I743ffd6058982f8f182ea4d73172a029967f3ea5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32408
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
2019-07-02 14:11:31 +00:00
Martin Roth 5c354b9979 soc/amd/picasso: Create picasso as a copy of stoneyridge
So that everyone can see what's being updated from stoney, we're
starting with a direct copy of the stoney directory. There are
arguments both for and against doing it this way, but I believe
This the most transparent way.  We've moved much of the duplicated
stoney code into the soc/amd/common directory and will continue
that work as it becomes obvious that we have unchanged code between
the SOCs.

Makefile.inc has been renamed as makefile.inc so that it won't
build in jenkins until the directory is  updated.

Other than that change, this is an exact copy of the stoneyridge
SOC directory which will be updated in the follow-on commits in
the patch train.

TEST=None
BUG=b:130804851

Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: I6809bd1eea304f76dd9000c079b3ed09f94dbd3b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32407
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-02 14:11:11 +00:00
Kevin Chiu 76378b3c01 mb/google/reef/variants/: fix Samsung K4F6E3S4HM-MGCJ density
Samsung K4F6E3S4HM-MGCJ density is 16Gb

BUG=b:121228792
BRANCH=master
TEST=emerge-snappy coreboot chromeos-bootimage
     MemTotal: 8041964kB in /proc/meminfo
Change-Id: Ie8ecd82b92d4e82d3955cf773febca30f6280a5e
Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33795
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2019-07-02 13:39:19 +00:00
Kyösti Mälkki fb49379ed2 device/pci_rom: Fix redundant pci_rom_probe() calls
For the PCI_VENDOR_ID_ATI case, we can rely on
pci_rom_acpi_fill_vfct() to make the call if necessary.

For hardware other than ATI, pci_rom_probe() was already
called from pci_rom_ssdt() and pci_dev_init(), so
PCI_ROM_ADDRESS BAR is already enabled, if requested so.

Change-Id: I0ea893a9ac7ba480840ebf5570d8fe0d9e20938f
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33909
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Mike Banon <mikebdp2@gmail.com>
2019-07-02 09:10:03 +00:00
Kyösti Mälkki 8c9be43271 device/pci_rom: Fix on-board optionrom address
The function pci_rom_probe() may be called multiple times
for a device. For cases where CBFS does not contain optionrom
file, only the first time probing for the on-board ROM
chip worked.

PCI_ROM_ADDRESS_ENABLE is set on the first run. Mask out all
the reserved bits of PCI_ROM_ADDRESS register to get correct
physical address for rom_header.

Change-Id: I14374954af09201494bf2f13e5a6e4dc640c05ee
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33908
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Mike Banon <mikebdp2@gmail.com>
2019-07-02 09:09:22 +00:00
Patrick Rudolph a19b07fec1 security/memory: Clear memory in ramstage
* Add architecture independend way of clearing all DRAM
* Implemented in ramstage as MTRRs need to be set to speed up
  clearing. Takes up to 15 seconds per GiB otherwise.
* Use memset_pae on x86
* Add quirks for FSP1.0

Tested on P8H61M-Pro:
* Clears 4GiB in less than 1 second
Tested on wedge100s:
* Clears 8GiB in 2 seconds

Change-Id: Idaadb8fb438e5b95557c0f65a14534e8762fde20
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31550
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-02 08:46:00 +00:00
Patrick Rudolph c1b7e8a60b cpu/x86/pae/pgtbl: Add memset with PAE
To clear all DRAM on x86_32, add a new method that uses PAE to access
more than 32bit of address space.
Add Documentation as well.

Required for clearing all system memory as part of security API.

Tested on wedge100s:
 Takes less than 2 seconds to clear 8GiB of DRAM.
Tested on P8H61M-Pro:
 Takes less than 1 second to clear 4GiB of DRAM.

Change-Id: I00f7ecf87b5c9227a9d58a0b61eecc38007e1a57
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31549
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-02 08:45:50 +00:00
Subrata Banik c796a8f238 soc/intel/icelake: Disable HDA based on devicetree
Change-Id: I28c2beca4bc26ddb896e68886571ebdc82276b48
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33933
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2019-07-02 02:32:23 +00:00
T Michael Turney 24e52659a3 QC common: fix compiler complaint, missing <string.h>
Change-Id: I5b5b7bc61dd82fb1b866857d60926b057fae3715
Signed-off-by: T Michael Turney <mturney@codeaurora.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33445
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-02 01:32:19 +00:00
You-Cheng Syu 1430b3995f util/cbmem: Update banner string regular expression
Banner string format has been changed (CB:30935). We should update our
regular expression correspondingly.

Also add "verstage" into the stage search list since some boards (e.g.,
Kukui) might start console initialization at verstage.

Change-Id: I16eba3ac5e203e80b0bfd42a4294401dbccd4463
Signed-off-by: You-Cheng Syu <youcheng@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33779
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2019-07-01 21:21:57 +00:00
Jacob Garber 02b1e20f00 util/ifdtool: Enable -Wmissing-prototypes
Change-Id: Idc31144024f785a42cbad78bf2c965d08dcc5178
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33861
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2019-07-01 14:30:53 +00:00
Jacob Garber 595d926bc2 util/ifdtool: Make internal functions static
These functions are only used in ifdtool, so they can be made static.

Change-Id: Ia48bfecb89a7445dbd0f140acb5ac0592da2ebe7
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33860
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2019-07-01 14:30:42 +00:00
Pandya, Varshit B 36cc664bc7 util/cbfstool/ifittool: use strtol function instead of atoi
Fix error "Invalid option -A" by adding "A" to options list.

Also, atoi does not parse hex string, for instance 0x200 is interpreted as 0,
and this causes a failure when updating second FIT table using -j option.
Use strtol instead of atoi

BUG=none
BRANCH=none
TEST=Build and boot hatch after enabling dual bootblock feature.

Change-Id: Ib227437f88ffcccda1ce2f20a9ab098e5aa091c7
Signed-off-by: Pandya, Varshit B <varshit.b.pandya@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33937
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2019-07-01 13:44:48 +00:00
Felix Singer b6b5e7fb45 mb/up/squared: Add kernel cmdline parameters
Since ttyS0 isn't used for UART0, configure ttyS4 as default

Change-Id: Ia0469226253b08328807d5401c05633296e43d22
Signed-off-by: Felix Singer <felix.singer@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33785
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-01 12:28:28 +00:00
Arthur Heymans a449290ca2 Use 3rdparty/intel-microcode
Instead of maintaining this in 3rdparty/blobs use the
3rdparty/intel-microcode which is maintained by Intel.

This allows for some finegrained control where family+model span
multiple targets.

Microcode updates present in
3rdparty/blobs/soc/intel/{baytrail,broadwell} are left out since those
contain updates not present in the Intel repo. Those are presumably
early CPU samples that did not end up in products.

The following MCU are get a new revision:
old:
 sig 0x000306c3, pf_mask 0x32, 2018-04-02, rev 0x0025, size 23552
 sig 0x00040651, pf_mask 0x72, 2018-04-02, rev 0x0024, size 22528
 sig 0x000206a7, pf_mask 0x12, 2018-04-10, rev 0x002e, size 12288
 sig 0x000306a9, pf_mask 0x12, 2018-04-10, rev 0x0020, size 13312
 sig 0x000706a1, pf_mask 0x01, 2018-05-22, rev 0x0028, size 73728
 sig 0x000506c9, pf_mask 0x03, 2018-05-11, rev 0x0032, size 16384
 sig 0x000506ca, pf_mask 0x03, 2018-05-11, rev 0x000c, size 14336
 sig 0x000806e9, pf_mask 0xc0, 2018-03-24, rev 0x008e, size 98304
 sig 0x000906e9, pf_mask 0x2a, 2018-03-24, rev 0x008e, size 98304
 sig 0x000906ea, pf_mask 0x22, 2018-05-02, rev 0x0096, size 97280
 sig 0x000906eb, pf_mask 0x02, 2018-03-24, rev 0x008e, size 98304
 sig 0x00050665, pf_mask 0x10, 2018-04-20, rev 0xe00000a, size 18432
 sig 0x000506e3, pf_mask 0x36, 2018-04-17, rev 0x00c6, size 99328
 sig 0x000906e9, pf_mask 0x2a, 2018-03-24, rev 0x008e, size 98304
 sig 0x000406e3, pf_mask 0xc0, 2018-04-17, rev 0x00c6, size 99328

new:
 sig 0x000306c3, pf_mask 0x32, 2019-02-26, rev 0x0027, size 23552
 sig 0x00040651, pf_mask 0x72, 2019-02-26, rev 0x0025, size 21504
 sig 0x000206a7, pf_mask 0x12, 2019-02-17, rev 0x002f, size 12288
 sig 0x000306a9, pf_mask 0x12, 2019-02-13, rev 0x0021, size 14336
 sig 0x000706a1, pf_mask 0x01, 2019-01-02, rev 0x002e, size 73728
 sig 0x000506c9, pf_mask 0x03, 2019-01-15, rev 0x0038, size 17408
 sig 0x000506ca, pf_mask 0x03, 2019-03-01, rev 0x0016, size 15360
 sig 0x000806e9, pf_mask 0xc0, 2019-04-01, rev 0x00b4, size 99328
 sig 0x000906e9, pf_mask 0x2a, 2019-04-01, rev 0x00b4, size 99328
 sig 0x000906ea, pf_mask 0x22, 2019-04-01, rev 0x00b4, size 98304
 sig 0x000906eb, pf_mask 0x02, 2019-04-01, rev 0x00b4, size 99328
 sig 0x00050665, pf_mask 0x10, 2019-03-23, rev 0xe00000d, size 19456
 sig 0x000506e3, pf_mask 0x36, 2019-04-01, rev 0x00cc, size 100352
 sig 0x000906e9, pf_mask 0x2a, 2019-04-01, rev 0x00b4, size 99328
 sig 0x000406e3, pf_mask 0xc0, 2019-04-01, rev 0x00cc, size 100352

Change-Id: Idcfb3c3c774e0b47637e1b5308c28002aa044f1c
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33554
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-07-01 10:26:12 +00:00
Frans Hendriks 3891d272a0 security/tpm/tss/tcg-2.0/tss.c: Add debug message to tlcl_lib_init()
No message is reported in tlcl_lib_init() when tis_init() or tis_open()
returned an error value.
Add debug string.

BUG=N/A
TEST=Build binary and verified logging on Facebook FBG-1701

Change-Id: I522e488ddd3a1bd94a1a8c8470c757bd79c6d5c5
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33415
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2019-07-01 08:31:26 +00:00
Pavel Sayekat 40dc75efcb util/superiotool/nuvoton.c: Minor tag update/removal
Signed-off-by: Pavel Sayekat <pavelsayekat@gmail.com>
Change-Id: Ic193f31b9776683849578bf9009c51bf22d1dae6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33910
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2019-07-01 08:30:44 +00:00
Kyösti Mälkki 6bdaaefb30 intel/fsp_rangeley: Use fixed FSB/BCLK value 100 MHz
Prior to commit
  d731a24 src/cpu/intel: Set get_ia32_fsb function common

value of 200 was silently used as a default for fsp_rangeley
(model_406dx) in cpu/x86/lapic/apic_timer:set_timer_fsb().

After the commit, get_ia32_fsb() returns -2, eventually
resulting with divide-by-zero in timer_monotonic_get(), as
get_timer_fsb() returns 0.

Add Rangeley CPUID model 0x4d to get_ia32_fsb() as a fix,
using BCLK = 100 MHz based on the comments in
  northbridge/intel/fsp_rangeley/udelay.c

Change-Id: I306f85dba9b1e91539fc0ecc9b2ae9d54f82be6c
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33822
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2019-07-01 04:18:41 +00:00
Subrata Banik 86dbe0f307 Kconfig: Enable RAMPAYLOAD for x86
This patch makes CONFIG_RAMPAYLOAD default enable upon selection
of HAVE_RAMPAYLOAD kconfig from mainboard for x86 platform.

Without this CL, CONFIG_RAMPAYLOAD is still disabled although
mainboard has selected CONFIG_HAVE_RAMPAYLOAD.

Change-Id: I40308bbf970a0dbe5f7e2086ed8a7a70c2a3a32c
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33859
Reviewed-by: ron minnich <rminnich@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-01 02:27:38 +00:00
Marshall Dawson ab0ab966f5 pci_ids.h: Add AMD Picasso IDs
Change-Id: I4ac67d1577229e63424dd7fd0ff84d1acfe826c3
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33748
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
2019-06-30 18:40:13 +00:00
Julius Werner ce4d39d2d7 libpayload: cbgfx: Run cbgfx_init() before we need it for draw_box()
calculate_color() uses the 'fbinfo' global that is initialized by
cbgfx_init(), so we need to run the latter before we can run the former
or we get a null pointer access.

Change-Id: I73ca8e20ca36f64d699379d504fd41dc2084f157
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33855
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
2019-06-29 00:31:14 +00:00
Jacob Garber c22ebc9339 sb/amd/sb{700,800}: Clean up index manipulations
It looks like in days gone by that these switches were once parts of
loops that incremented 'index' as they went along. However, we don't
have any loops anymore, so remove the needless increments and streamline
the rest of the assignments.

Change-Id: Iaabee984333c273af7810f9c11ed26bbb2a995d1
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Found-by: scan-build 8.0.0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33774
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-06-28 19:36:11 +00:00
Jacob Garber 464f4d6ee2 device: Tidy up add_more_links()
- Add documentation comment
- Use 'unsigned int' to make checkpatch happy
- Return early if no more links need to be added
- Add error handling if malloc fails
- Clean up whitespace

Change-Id: I70976ee2539b058721d0ae3c15edf279253cd9b7
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Found-by: Coverity CID 1229634
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33238
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-06-28 19:32:18 +00:00