00003ae712
during early coreboot_ram), pci_{read,write}_config{8,16,32} will die().
This patch changes pci_{read,write}_config{8,16,32} to use the existing
PCI access method autodetection infrastructure instead of die()ing.
Until r4340, any usage of pci_{read,write}_config{8,16,32} in
coreboot_ram before the device tree was set up resulted in either a
silent hang or a NULL pointer dereference. I changed the code in r4340
to die() properly with a loud error message. That still was not perfect,
but at least it allowed people to see why their new ports died.
Still, die() is not something developers like to see, and thus a patch
to automatically pick a sensible default instead of dying was created.
Of course, handling PCI access method selection automatically for
fallback purposes has certain limitations before the device tree is set
up. We only check if conf1 works and use conf2 as fallback. No further
tests are done.
This patch enables cleanups and readability improvements in early
coreboot_ram code:
Without this patch:
dword = pci_cf8_conf1.read32(&pbus, sm_dev->bus->secondary,
sm_dev->path.pci.devfn, 0x64);
With this patch:
dword = pci_read_config32(sm_dev, 0x64);
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4646 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
129 lines
4.1 KiB
C
129 lines
4.1 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2004 Linux Networx
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* (Written by Eric Biederman <ebiederman@lnxi.com> for Linux Networx)
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* Copyright (C) 2009 coresystems GmbH
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include <console/console.h>
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#include <arch/pciconf.h>
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#include <device/pci.h>
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#include <device/pci_ids.h>
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#include <device/pci_ops.h>
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/* The only consumer of the return value of get_pbus() is ops_pci_bus().
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* ops_pci_bus() can handle being passed NULL and auto-picks working ops.
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*/
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static struct bus *get_pbus(device_t dev)
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{
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struct bus *pbus = NULL;
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if (!dev)
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die("get_pbus: dev is NULL!\n");
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else
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pbus = dev->bus;
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while(pbus && pbus->dev && !ops_pci_bus(pbus)) {
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if (pbus == pbus->dev->bus) {
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printk_alert("%s in endless loop looking for a parent "
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"bus with ops_pci_bus for %s, breaking out.\n",
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__func__, dev_path(dev));
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break;
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}
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pbus = pbus->dev->bus;
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}
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if (!pbus || !pbus->dev || !pbus->dev->ops || !pbus->dev->ops->ops_pci_bus) {
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/* This can happen before the device tree is set up completely. */
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//printk_emerg("%s: Cannot find pci bus operations.\n", dev_path(dev));
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pbus = NULL;
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}
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return pbus;
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}
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uint8_t pci_read_config8(device_t dev, unsigned where)
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{
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struct bus *pbus = get_pbus(dev);
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return ops_pci_bus(pbus)->read8(pbus, dev->bus->secondary, dev->path.pci.devfn, where);
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}
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uint16_t pci_read_config16(device_t dev, unsigned where)
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{
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struct bus *pbus = get_pbus(dev);
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return ops_pci_bus(pbus)->read16(pbus, dev->bus->secondary, dev->path.pci.devfn, where);
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}
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uint32_t pci_read_config32(device_t dev, unsigned where)
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{
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struct bus *pbus = get_pbus(dev);
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return ops_pci_bus(pbus)->read32(pbus, dev->bus->secondary, dev->path.pci.devfn, where);
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}
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void pci_write_config8(device_t dev, unsigned where, uint8_t val)
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{
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struct bus *pbus = get_pbus(dev);
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ops_pci_bus(pbus)->write8(pbus, dev->bus->secondary, dev->path.pci.devfn, where, val);
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}
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void pci_write_config16(device_t dev, unsigned where, uint16_t val)
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{
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struct bus *pbus = get_pbus(dev);
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ops_pci_bus(pbus)->write16(pbus, dev->bus->secondary, dev->path.pci.devfn, where, val);
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}
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void pci_write_config32(device_t dev, unsigned where, uint32_t val)
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{
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struct bus *pbus = get_pbus(dev);
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ops_pci_bus(pbus)->write32(pbus, dev->bus->secondary, dev->path.pci.devfn, where, val);
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}
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#if CONFIG_MMCONF_SUPPORT
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uint8_t pci_mmio_read_config8(device_t dev, unsigned where)
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{
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struct bus *pbus = get_pbus(dev);
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return pci_ops_mmconf.read8(pbus, dev->bus->secondary, dev->path.pci.devfn, where);
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}
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uint16_t pci_mmio_read_config16(device_t dev, unsigned where)
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{
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struct bus *pbus = get_pbus(dev);
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return pci_ops_mmconf.read16(pbus, dev->bus->secondary, dev->path.pci.devfn, where);
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}
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uint32_t pci_mmio_read_config32(device_t dev, unsigned where)
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{
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struct bus *pbus = get_pbus(dev);
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return pci_ops_mmconf.read32(pbus, dev->bus->secondary, dev->path.pci.devfn, where);
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}
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void pci_mmio_write_config8(device_t dev, unsigned where, uint8_t val)
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{
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struct bus *pbus = get_pbus(dev);
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pci_ops_mmconf.write8(pbus, dev->bus->secondary, dev->path.pci.devfn, where, val);
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}
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void pci_mmio_write_config16(device_t dev, unsigned where, uint16_t val)
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{
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struct bus *pbus = get_pbus(dev);
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pci_ops_mmconf.write16(pbus, dev->bus->secondary, dev->path.pci.devfn, where, val);
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}
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void pci_mmio_write_config32(device_t dev, unsigned where, uint32_t val)
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{
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struct bus *pbus = get_pbus(dev);
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pci_ops_mmconf.write32(pbus, dev->bus->secondary, dev->path.pci.devfn, where, val);
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}
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#endif
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