7e78e56c34
I2C0&1 are either not available or not functional. Add place holders instead, so that the array index matches the I2C controller number. I2C4 is slave device only, so do not initialize it as I2C host controller. Also do some slight refactoring. BUG=b:153152871 BUG=b:153675916 Change-Id: I397b074ef9c14bf6a4f6680696582f5173a5d0d3 Signed-off-by: Martin Roth <martinroth@chromium.org> Signed-off-by: Paul Ma <magf@bitland.corp-partner.google.com> Signed-off-by: Raul E Rangel <rrangel@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1897071 Reviewed-on: https://chromium-review.googlesource.com/2057468 Reviewed-on: https://chromium-review.googlesource.com/2094855 Reviewed-on: https://chromium-review.googlesource.com/2149870 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40247 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
40 lines
1.2 KiB
C
40 lines
1.2 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/* This file is part of the coreboot project. */
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#ifndef __PICASSO_CHIP_H__
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#define __PICASSO_CHIP_H__
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#include <stddef.h>
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#include <stdint.h>
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#include <commonlib/helpers.h>
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#include <drivers/i2c/designware/dw_i2c.h>
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#include <soc/i2c.h>
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#include <soc/iomap.h>
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#include <arch/acpi_device.h>
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struct soc_amd_picasso_config {
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/*
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* If sb_reset_i2c_slaves() is called, this devicetree register
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* defines which I2C SCL will be toggled 9 times at 100 KHz.
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* For example, should we need I2C0 and I2C3 have their slave
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* devices reseted by toggling SCL, use:
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*
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* register i2c_scl_reset = (GPIO_I2C0_SCL | GPIO_I2C3_SCL)
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*/
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u8 i2c_scl_reset;
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struct dw_i2c_bus_config i2c[I2C_MASTER_DEV_COUNT];
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enum {
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I2S_PINS_MAX_HDA = 0, /* HDA w/reset 3xSDI, SW w/Data0 */
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I2S_PINS_MAX_MHDA = 1, /* HDA no reset 3xSDI, SW w/Data0-1 */
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I2S_PINS_MIN_HDA = 2, /* HDA w/reset 1xSDI, SW w/Data0-2 */
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I2S_PINS_MIN_MHDA = 3, /* HDA no reset 1xSDI, SW w/Data0-3 */
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I2S_PINS_I2S_TDM = 4,
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I2S_PINS_UNCONF = 7, /* All pads will be input mode */
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} acp_pin_cfg;
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};
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typedef struct soc_amd_picasso_config config_t;
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extern struct device_operations pci_domain_ops;
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#endif /* __PICASSO_CHIP_H__ */
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