9cb5dcb40c
1. Remove dmi.h as it's migrated as gpmr.header 2. Remove unused gpmr definitions 3. For old platforms, define DMI defintions in c code for less code changes. TEST=Build Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com> Change-Id: Ib340ff1ab7fd88b1e7b3860ffec055a75e562de7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63472 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
67 lines
1.9 KiB
C
67 lines
1.9 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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#include <bootblock_common.h>
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#include <device/pci_def.h>
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#include <device/pci_ops.h>
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#include <intelblocks/lpc_lib.h>
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#include <intelblocks/pcr.h>
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#include <soc/intel/common/block/lpc/lpc_def.h>
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#include <soc/pci_devs.h>
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#include <soc/pcr_ids.h>
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#include <superio/aspeed/ast2400/ast2400.h>
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#include <superio/aspeed/common/aspeed.h>
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#include <cpxsp_dl_gpio.h>
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#define ASPEED_SIO_PORT 0x2E
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#define PCR_DMI_LPCIOD 0x2770
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#define PCR_DMI_LPCIOE 0x2774
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static void enable_espi_lpc_io_windows(void)
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{
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/*
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* Set up decoding windows on PCH over PCR. The CPUs use two of AST2500 SIO ports,
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* one is connected to debug header (SUART1) and another is used as SOL (SUART2).
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* For that end it is wired into BMC virtual port.
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*/
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uint16_t lpciod = (LPC_IOD_COMB_RANGE | LPC_IOD_COMA_RANGE);
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uint16_t lpcioe = (LPC_IOE_SUPERIO_2E_2F | LPC_IOE_COMB_EN | LPC_IOE_COMA_EN);
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/* Open IO windows: 0x3f8 for com1 and 02e8 for com2 */
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pcr_or32(PID_DMI, PCR_DMI_LPCIOD, lpciod);
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/* LPC I/O enable: com1 and com2 */
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pcr_or32(PID_DMI, PCR_DMI_LPCIOE, lpcioe);
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/* Enable com1 (0x3f8), com2 (02f8) and superio (0x2e) */
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pci_write_config16(PCH_DEV_LPC, LPC_IO_DECODE, lpciod);
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pci_write_config16(PCH_DEV_LPC, LPC_IO_ENABLES, lpcioe);
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}
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static uint8_t com_to_ast_sio(uint8_t com)
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{
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switch (com) {
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case 0:
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return AST2400_SUART1;
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case 1:
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return AST2400_SUART2;
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case 2:
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return AST2400_SUART3;
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case 4:
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return AST2400_SUART4;
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default:
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return AST2400_SUART1;
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}
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}
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void bootblock_mainboard_early_init(void)
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{
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/* pre-configure Lewisburg PCH GPIO pads */
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gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table));
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/* Open IO windows */
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enable_espi_lpc_io_windows();
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/* Configure appropriate physical port of SuperIO chip off BMC */
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const pnp_devfn_t serial_dev = PNP_DEV(ASPEED_SIO_PORT,
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com_to_ast_sio(CONFIG_UART_FOR_CONSOLE));
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aspeed_enable_serial(serial_dev, CONFIG_TTYS0_BASE);
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}
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