Jonathan Neuschäfer 5135f1184d RISC-V boards: Remove PAGETABLES section from memlayout.ld ... RISC-V doesn't set up page tables anymore, since commit b26759d703 ("arch/riscv: Don't set up virtual memory"). Change-Id: Id1e759b63fb0bc88ab256994d3849d16814affa0 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/25701 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>		2018-04-27 09:07:43 +00:00
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acpi	…
arch	RISC-V boards: Remove PAGETABLES section from memlayout.ld	2018-04-27 09:07:43 +00:00
commonlib	compiler.h: add __weak macro	2018-04-24 14:37:59 +00:00
console	compiler.h: add __weak macro	2018-04-24 14:37:59 +00:00
cpu	cpu/x86: add limited runtime identity page mapping	2018-04-26 06:55:59 +00:00
device	device: Add flag to disable PCIe ASPM	2018-04-26 21:32:48 +00:00
drivers	drivers/uart: Allow the 8250IO driver only on x86	2018-04-27 09:05:45 +00:00
ec	compiler.h: add __weak macro	2018-04-24 14:37:59 +00:00
include	device: Add flag to disable PCIe ASPM	2018-04-26 21:32:48 +00:00
lib	lib/ext_stage_cache: include prog arg in stage cache metadata	2018-04-24 14:39:36 +00:00
mainboard	RISC-V boards: Remove PAGETABLES section from memlayout.ld	2018-04-27 09:07:43 +00:00
northbridge	vx900: Drop some unused defines	2018-04-25 11:43:04 +00:00
security	security/vboot: Add function to check if UDC can be enabled	2018-04-27 02:51:32 +00:00
soc	soc/intel/common/block/xdci: Use vboot_can_enable_udc in xdci_can_enable	2018-04-27 02:51:40 +00:00
southbridge	compiler.h: add __weak macro	2018-04-24 14:37:59 +00:00
superio	Intel i3100 boards & chips: Remove - using LATE_CBMEM_INIT	2018-01-15 23:25:12 +00:00
vendorcode	vendorcode/intel: Update GLK FSP Header files w.r.t FSP v2.0.2	2018-04-27 03:25:43 +00:00
Kconfig	Timestamps: Add option to print timestamps to debug console	2018-03-09 17:16:21 +00:00