add76f91d5
Also, extra-lines added or removed and local includes moved down. Change-Id: I5e739233f3742fd68d537f671642bb04886e3009 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32009 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
59 lines
1.5 KiB
C
59 lines
1.5 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2016 Intel Corporation.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <cf9_reset.h>
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#include <console/console.h>
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#include <fsp/util.h>
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#include <intelblocks/pmclib.h>
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#include <soc/intel/common/reset.h>
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#include <soc/me.h>
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#include <soc/pm.h>
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static void do_force_global_reset(void)
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{
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/*
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* BIOS should ensure it does a global reset
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* to reset both host and Intel ME by setting
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* PCH PMC [B0:D31:F2 register offset 0x1048 bit 20]
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*/
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pmc_global_reset_enable(true);
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/* Now BIOS can write 0x06 or 0x0E to 0xCF9 port
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* to global reset platform */
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do_full_reset();
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}
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void do_global_reset(void)
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{
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if (send_global_reset() != 0) {
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/* If ME unable to reset platform then
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* force global reset using PMC CF9GR register*/
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do_force_global_reset();
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}
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}
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void chipset_handle_reset(uint32_t status)
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{
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switch (status) {
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case FSP_STATUS_RESET_REQUIRED_3: /* Global Reset */
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printk(BIOS_DEBUG, "GLOBAL RESET!!\n");
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global_reset();
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break;
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default:
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printk(BIOS_ERR, "unhandled reset type %x\n", status);
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die("unknown reset type");
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break;
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}
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}
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