6b5bc77c9b
Stefan thinks they don't add value. Command used: sed -i -e '/file is part of /d' $(git grep "file is part of " |egrep ":( */\*.*\*/\$|#|;#|-- | *\* )" | cut -d: -f1 |grep -v crossgcc |grep -v gcov | grep -v /elf.h |grep -v nvramtool) The exceptions are for: - crossgcc (patch file) - gcov (imported from gcc) - elf.h (imported from GNU's libc) - nvramtool (more complicated header) The removed lines are: - fmt.Fprintln(f, "/* This file is part of the coreboot project. */") -# This file is part of a set of unofficial pre-commit hooks available -/* This file is part of coreboot */ -# This file is part of msrtool. -/* This file is part of msrtool. */ - * This file is part of ncurses, designed to be appended after curses.h.in -/* This file is part of pgtblgen. */ - * This file is part of the coreboot project. - /* This file is part of the coreboot project. */ -# This file is part of the coreboot project. -# This file is part of the coreboot project. -## This file is part of the coreboot project. --- This file is part of the coreboot project. -/* This file is part of the coreboot project */ -/* This file is part of the coreboot project. */ -;## This file is part of the coreboot project. -# This file is part of the coreboot project. It originated in the - * This file is part of the coreinfo project. -## This file is part of the coreinfo project. - * This file is part of the depthcharge project. -/* This file is part of the depthcharge project. */ -/* This file is part of the ectool project. */ - * This file is part of the GNU C Library. - * This file is part of the libpayload project. -## This file is part of the libpayload project. -/* This file is part of the Linux kernel. */ -## This file is part of the superiotool project. -/* This file is part of the superiotool project */ -/* This file is part of uio_usbdebug */ Change-Id: I82d872b3b337388c93d5f5bf704e9ee9e53ab3a9 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41194 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
62 lines
1.4 KiB
Text
62 lines
1.4 KiB
Text
/*
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*
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*
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* SPDX-License-Identifier: GPL-2.0-or-later
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*/
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#include <acpi/acpi.h>
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#include "variant/ec.h"
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#include "variant/gpio.h"
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DefinitionBlock(
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"dsdt.aml",
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"DSDT",
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0x02, // DSDT revision: ACPI v2.0 and up
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OEM_ID,
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ACPI_TABLE_CREATOR,
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0x20110725 // OEM revision
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)
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{
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#include <soc/intel/tigerlake/acpi/platform.asl>
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// global NVS and variables
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#include <soc/intel/common/block/acpi/acpi/globalnvs.asl>
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// CPU
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#include <cpu/intel/common/acpi/cpu.asl>
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Scope (\_SB) {
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Device (PCI0)
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{
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#include <soc/intel/common/block/acpi/acpi/northbridge.asl>
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#include <soc/intel/tigerlake/acpi/southbridge.asl>
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#include <soc/intel/tigerlake/acpi/tcss.asl>
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}
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/* Mainboard hooks */
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#include "mainboard.asl"
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}
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// Chrome OS specific
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#include <vendorcode/google/chromeos/acpi/chromeos.asl>
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/* Include Low power idle table for a short term workaround to enable
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S0ix. Once cr50 pulse width is fixed, this can be removed. */
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#include <soc/intel/common/acpi/lpit.asl>
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// Chrome OS Embedded Controller
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Scope (\_SB.PCI0.LPCB)
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{
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// ACPI code for EC SuperIO functions
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#include <ec/google/chromeec/acpi/superio.asl>
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// ACPI code for EC functions
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#include <ec/google/chromeec/acpi/ec.asl>
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}
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#include <southbridge/intel/common/acpi/sleepstates.asl>
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#if CONFIG(VARIANT_HAS_MIPI_CAMERA)
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/* Camera */
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#include <soc/intel/tigerlake/acpi/ipu.asl>
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#include <variant/acpi/mipi_camera.asl>
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#endif /* VARIANT_HAS_MIPI_CAMERA */
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}
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