e1163c1782
Change-Id: I4a4ee99468e5f1dae8412ae565a34290493db726 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/6201 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins)
223 lines
5.8 KiB
C
223 lines
5.8 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2011 Advanced Micro Devices, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#ifndef BIOS_SIZE
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#define BIOS_SIZE 0x04 //04 - 1MB
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#endif
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#define LEGACY_FREE 0x00
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#if !CONFIG_ONBOARD_USB30
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#define XHCI_SUPPORT 0x01
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#endif
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//#define ACPI_SLEEP_TRAP 0x01 // No sleep trap smi support in coreboot.
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//#define SPREAD_SPECTRUM_EPROM_LOAD 0x01
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/**
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* Module Specific Defines for platform BIOS
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*
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*/
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/**
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* PCIEX_BASE_ADDRESS - Define PCIE base address
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*
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* @param[Option] MOVE_PCIEBAR_TO_F0000000 Set PCIe base address to 0xF7000000
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*/
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#ifdef MOVE_PCIEBAR_TO_F0000000
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#define PCIEX_BASE_ADDRESS 0xF7000000
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#else
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#define PCIEX_BASE_ADDRESS 0xE0000000
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#endif
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/**
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* SMBUS0_BASE_ADDRESS - Smbus base address
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*
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*/
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#ifndef SMBUS0_BASE_ADDRESS
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#define SMBUS0_BASE_ADDRESS 0xB00
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#endif
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/**
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* SMBUS1_BASE_ADDRESS - Smbus1 (ASF) base address
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*
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*/
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#ifndef SMBUS1_BASE_ADDRESS
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#define SMBUS1_BASE_ADDRESS 0xB20
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#endif
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/**
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* SIO_PME_BASE_ADDRESS - Super IO PME base address
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*
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*/
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#ifndef SIO_PME_BASE_ADDRESS
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#define SIO_PME_BASE_ADDRESS 0xE00
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#endif
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/**
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* SPI_BASE_ADDRESS - SPI controller (ROM) base address
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*
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*/
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#ifndef SPI_BASE_ADDRESS
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#define SPI_BASE_ADDRESS 0xFEC10000
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#endif
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/**
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* WATCHDOG_TIMER_BASE_ADDRESS - WATCHDOG timer base address
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*
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*/
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#ifndef WATCHDOG_TIMER_BASE_ADDRESS
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#define WATCHDOG_TIMER_BASE_ADDRESS 0xFEC000F0 // Watchdog Timer Base Address
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#endif
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/**
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* HPET_BASE_ADDRESS - HPET base address
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*
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*/
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#ifndef HPET_BASE_ADDRESS
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#define HPET_BASE_ADDRESS 0xFED00000 // HPET Base address
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#endif
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/**
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* ALT_ADDR_400 - For some BIOS codebases which use 0x400 as ACPI base address
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*
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*/
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#ifdef ALT_ADDR_400
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#define ACPI_BLK_BASE 0x400
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#else
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#define ACPI_BLK_BASE 0x800
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#endif
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#define PM1_STATUS_OFFSET 0x00
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#define PM1_ENABLE_OFFSET 0x02
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#define PM1_CONTROL_OFFSET 0x04
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#define PM_TIMER_OFFSET 0x08
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#define CPU_CONTROL_OFFSET 0x10
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#define EVENT_STATUS_OFFSET 0x20
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#define EVENT_ENABLE_OFFSET 0x24
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/**
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* PM1_EVT_BLK_ADDRESS - ACPI power management Event Block base address
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*
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*/
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#define PM1_EVT_BLK_ADDRESS ACPI_BLK_BASE + PM1_STATUS_OFFSET // AcpiPm1EvtBlkAddr
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/**
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* PM1_CNT_BLK_ADDRESS - ACPI power management Control block base address
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*
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*/
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#define PM1_CNT_BLK_ADDRESS ACPI_BLK_BASE + PM1_CONTROL_OFFSET // AcpiPm1CntBlkAddr
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/**
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* PM1_TMR_BLK_ADDRESS - ACPI power management Timer block base address
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*
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*/
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#define PM1_TMR_BLK_ADDRESS ACPI_BLK_BASE + PM_TIMER_OFFSET // AcpiPmTmrBlkAddr
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/**
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* CPU_CNT_BLK_ADDRESS - ACPI power management CPU Control block base address
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*
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*/
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#define CPU_CNT_BLK_ADDRESS ACPI_BLK_BASE + CPU_CONTROL_OFFSET // CpuControlBlkAddr
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/**
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* GPE0_BLK_ADDRESS - ACPI power management General Purpose Event block base address
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*
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*/
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#define GPE0_BLK_ADDRESS ACPI_BLK_BASE + EVENT_STATUS_OFFSET // AcpiGpe0BlkAddr
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/**
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* SMI_CMD_PORT - ACPI SMI Command block base address
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*
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*/
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#define SMI_CMD_PORT 0xB0 // SmiCmdPortAddr
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/**
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* ACPI_PMA_CNT_BLK_ADDRESS - ACPI power management additional control block base address
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*
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*/
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#define ACPI_PMA_CNT_BLK_ADDRESS 0xFE00 // AcpiPmaCntBlkAddr
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/**
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* SATA_IDE_MODE_SSID - Sata controller IDE mode SSID.
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* Define value for SSID while SATA controller set to IDE mode.
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*/
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#define SATA_IDE_MODE_SSID 0x78001022
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/**
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* SATA_RAID_MODE_SSID - Sata controller RAID mode SSID.
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* Define value for SSID while SATA controller set to RAID mode.
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*/
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#define SATA_RAID_MODE_SSID 0x78021022
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/**
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* SATA_RAID5_MODE_SSID - Sata controller RAID5 mode SSID.
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* Define value for SSID while SATA controller set to RAID5 mode.
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*/
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#define SATA_RAID5_MODE_SSID 0x78031022
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/**
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* SATA_AHCI_MODE_SSID - Sata controller AHCI mode SSID.
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* Define value for SSID while SATA controller set to AHCI mode.
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*/
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#define SATA_AHCI_SSID 0x78011022
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/**
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* OHCI_SSID - All SB OHCI controllers SSID value.
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*
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*/
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#define OHCI_SSID 0x78071022
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/**
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* EHCI_SSID - All SB EHCI controllers SSID value.
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*
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*/
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#define EHCI_SSID 0x78081022
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/**
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* OHCI4_SSID - OHCI (USB 1.1 mode *HW force) controllers SSID value.
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*
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*/
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#define OHCI4_SSID 0x78091022
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/**
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* SMBUS_SSID - Smbus controller (South Bridge device 0x14 function 0) SSID value.
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*
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*/
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#define SMBUS_SSID 0x780B1022
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/**
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* IDE_SSID - SATA IDE controller (South Bridge device 0x14 function 1) SSID value.
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*
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*/
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#define IDE_SSID 0x780C1022
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/**
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* AZALIA_SSID - AZALIA controller (South Bridge device 0x14 function 2) SSID value.
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*
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*/
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#define AZALIA_SSID 0x780D1022
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/**
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* LPC_SSID - LPC controller (South Bridge device 0x14 function 3) SSID value.
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*
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*/
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#define LPC_SSID 0x780E1022
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/**
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* PCIB_SSID - PCIB controller (South Bridge device 0x14 function 4) SSID value.
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*
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*/
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#define PCIB_SSID 0x780F1022
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