59de6c9c71
Add a common southbridge gpio code to reduce existing duplicated code. By adding it to ram-stage, GPIOs can be changed any time, without the need of direct register access. The files are based on bd82x6x and lynxpoint gpio.c. Change-Id: Iaf0c2f941f2625a5547f9cba79da1b173da6f295 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/12893 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
188 lines
4 KiB
C
188 lines
4 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2011-2016 The Chromium OS Authors. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef INTEL_COMMON_GPIO_H
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#define INTEL_COMMON_GPIO_H
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#include <stdint.h>
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/* LPC GPIO Base Address Register */
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#define GPIO_BASE 0x48
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/* PCI Configuration Space (D31:F0): LPC */
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#define PCH_LPC_DEV PCI_DEV(0, 0x1f, 0)
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/* ICH7 GPIOBASE */
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#define GPIO_USE_SEL 0x00
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#define GP_IO_SEL 0x04
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#define GP_LVL 0x0c
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#define GPO_BLINK 0x18
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#define GPI_INV 0x2c
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#define GPIO_USE_SEL2 0x30
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#define GP_IO_SEL2 0x34
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#define GP_LVL2 0x38
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#define GPIO_USE_SEL3 0x40
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#define GP_IO_SEL3 0x44
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#define GP_LVL3 0x48
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#define GP_RST_SEL1 0x60
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#define GP_RST_SEL2 0x64
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#define GP_RST_SEL3 0x68
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#define GPIO_MODE_NATIVE 0
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#define GPIO_MODE_GPIO 1
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#define GPIO_MODE_NONE 1
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#define GPIO_DIR_OUTPUT 0
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#define GPIO_DIR_INPUT 1
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#define GPIO_NO_INVERT 0
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#define GPIO_INVERT 1
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#define GPIO_LEVEL_LOW 0
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#define GPIO_LEVEL_HIGH 1
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#define GPIO_NO_BLINK 0
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#define GPIO_BLINK 1
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#define GPIO_RESET_PWROK 0
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#define GPIO_RESET_RSMRST 1
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struct pch_gpio_set1 {
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u32 gpio0 : 1;
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u32 gpio1 : 1;
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u32 gpio2 : 1;
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u32 gpio3 : 1;
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u32 gpio4 : 1;
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u32 gpio5 : 1;
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u32 gpio6 : 1;
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u32 gpio7 : 1;
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u32 gpio8 : 1;
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u32 gpio9 : 1;
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u32 gpio10 : 1;
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u32 gpio11 : 1;
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u32 gpio12 : 1;
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u32 gpio13 : 1;
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u32 gpio14 : 1;
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u32 gpio15 : 1;
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u32 gpio16 : 1;
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u32 gpio17 : 1;
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u32 gpio18 : 1;
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u32 gpio19 : 1;
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u32 gpio20 : 1;
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u32 gpio21 : 1;
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u32 gpio22 : 1;
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u32 gpio23 : 1;
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u32 gpio24 : 1;
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u32 gpio25 : 1;
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u32 gpio26 : 1;
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u32 gpio27 : 1;
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u32 gpio28 : 1;
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u32 gpio29 : 1;
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u32 gpio30 : 1;
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u32 gpio31 : 1;
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} __attribute__ ((packed));
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struct pch_gpio_set2 {
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u32 gpio32 : 1;
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u32 gpio33 : 1;
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u32 gpio34 : 1;
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u32 gpio35 : 1;
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u32 gpio36 : 1;
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u32 gpio37 : 1;
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u32 gpio38 : 1;
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u32 gpio39 : 1;
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u32 gpio40 : 1;
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u32 gpio41 : 1;
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u32 gpio42 : 1;
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u32 gpio43 : 1;
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u32 gpio44 : 1;
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u32 gpio45 : 1;
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u32 gpio46 : 1;
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u32 gpio47 : 1;
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u32 gpio48 : 1;
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u32 gpio49 : 1;
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u32 gpio50 : 1;
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u32 gpio51 : 1;
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u32 gpio52 : 1;
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u32 gpio53 : 1;
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u32 gpio54 : 1;
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u32 gpio55 : 1;
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u32 gpio56 : 1;
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u32 gpio57 : 1;
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u32 gpio58 : 1;
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u32 gpio59 : 1;
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u32 gpio60 : 1;
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u32 gpio61 : 1;
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u32 gpio62 : 1;
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u32 gpio63 : 1;
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} __attribute__ ((packed));
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struct pch_gpio_set3 {
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u32 gpio64 : 1;
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u32 gpio65 : 1;
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u32 gpio66 : 1;
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u32 gpio67 : 1;
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u32 gpio68 : 1;
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u32 gpio69 : 1;
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u32 gpio70 : 1;
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u32 gpio71 : 1;
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u32 gpio72 : 1;
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u32 gpio73 : 1;
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u32 gpio74 : 1;
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u32 gpio75 : 1;
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} __attribute__ ((packed));
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struct pch_gpio_map {
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struct {
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const struct pch_gpio_set1 *mode;
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const struct pch_gpio_set1 *direction;
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const struct pch_gpio_set1 *level;
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const struct pch_gpio_set1 *reset;
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const struct pch_gpio_set1 *invert;
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const struct pch_gpio_set1 *blink;
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} set1;
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struct {
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const struct pch_gpio_set2 *mode;
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const struct pch_gpio_set2 *direction;
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const struct pch_gpio_set2 *level;
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const struct pch_gpio_set2 *reset;
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} set2;
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struct {
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const struct pch_gpio_set3 *mode;
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const struct pch_gpio_set3 *direction;
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const struct pch_gpio_set3 *level;
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const struct pch_gpio_set3 *reset;
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} set3;
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};
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extern const struct pch_gpio_map mainboard_gpio_map;
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/* Configure GPIOs with mainboard provided settings */
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void setup_pch_gpios(const struct pch_gpio_map *gpio);
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/* get GPIO pin value */
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int get_gpio(int gpio_num);
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/*
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* get a number comprised of multiple GPIO values. gpio_num_array points to
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* the array of gpio pin numbers to scan, terminated by -1.
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*/
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unsigned get_gpios(const int *gpio_num_array);
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void set_gpio(int gpio_num, int value);
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void clear_gpio(int gpio_num);
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int gpio_is_native(int gpio_num);
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#endif
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