536 lines
17 KiB
C
536 lines
17 KiB
C
/*
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*
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* Copyright (C) 2010 Patrick Georgi
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* Copyright (C) 2013 secunet Security Networks AG
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#ifndef __XHCI_PRIVATE_H
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#define __XHCI_PRIVATE_H
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//#define USB_DEBUG
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#include <usb/usb.h>
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#include <arch/barrier.h>
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#include <kconfig.h>
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//#define XHCI_DUMPS
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#define xhci_debug(fmt, args...) usb_debug("%s: " fmt, __func__, ## args)
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#ifdef XHCI_SPEW_DEBUG
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# define xhci_spew(fmt, args...) xhci_debug(fmt, ##args)
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#else
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# define xhci_spew(fmt, args...) do {} while(0)
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#endif
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#define MASK(startbit, lenbit) (((1<<(lenbit))-1)<<(startbit))
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/* Make these high enough to not collide with negative XHCI CCs */
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#define TIMEOUT -65
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#define CONTROLLER_ERROR -66
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#define COMMUNICATION_ERROR -67
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#define OUT_OF_MEMORY -68
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#define DRIVER_ERROR -69
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#define CC_SUCCESS 1
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#define CC_TRB_ERROR 5
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#define CC_STALL_ERROR 6
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#define CC_RESOURCE_ERROR 7
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#define CC_BANDWIDTH_ERROR 8
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#define CC_NO_SLOTS_AVAILABLE 9
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#define CC_SHORT_PACKET 13
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#define CC_EVENT_RING_FULL_ERROR 21
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#define CC_COMMAND_RING_STOPPED 24
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#define CC_COMMAND_ABORTED 25
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#define CC_STOPPED 26
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#define CC_STOPPED_LENGTH_INVALID 27
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enum {
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TRB_NORMAL = 1,
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TRB_SETUP_STAGE = 2, TRB_DATA_STAGE = 3, TRB_STATUS_STAGE = 4,
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TRB_LINK = 6, TRB_EVENT_DATA = 7,
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TRB_CMD_ENABLE_SLOT = 9, TRB_CMD_DISABLE_SLOT = 10, TRB_CMD_ADDRESS_DEV = 11,
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TRB_CMD_CONFIGURE_EP = 12, TRB_CMD_EVAL_CTX = 13, TRB_CMD_RESET_EP = 14,
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TRB_CMD_STOP_EP = 15, TRB_CMD_SET_TR_DQ = 16, TRB_CMD_NOOP = 23,
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TRB_EV_TRANSFER = 32, TRB_EV_CMD_CMPL = 33, TRB_EV_PORTSC = 34, TRB_EV_HOST = 37,
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};
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enum { TRB_TRT_NO_DATA = 0, TRB_TRT_OUT_DATA = 2, TRB_TRT_IN_DATA = 3 };
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enum { TRB_DIR_OUT = 0, TRB_DIR_IN = 1 };
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#define TRB_PORT_FIELD ptr_low
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#define TRB_PORT_START 24
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#define TRB_PORT_LEN 8
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#define TRB_TL_FIELD status /* TL - Transfer Length */
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#define TRB_TL_START 0
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#define TRB_TL_LEN 17
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#define TRB_EVTL_FIELD status /* EVTL - (Event TRB) Transfer Length */
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#define TRB_EVTL_START 0
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#define TRB_EVTL_LEN 24
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#define TRB_TDS_FIELD status /* TDS - TD Size */
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#define TRB_TDS_START 17
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#define TRB_TDS_LEN 5
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#define TRB_CC_FIELD status /* CC - Completion Code */
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#define TRB_CC_START 24
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#define TRB_CC_LEN 8
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#define TRB_C_FIELD control /* C - Cycle Bit */
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#define TRB_C_START 0
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#define TRB_C_LEN 1
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#define TRB_TC_FIELD control /* TC - Toggle Cycle */
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#define TRB_TC_START 1
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#define TRB_TC_LEN 1
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#define TRB_ENT_FIELD control /* ENT - Evaluate Next TRB */
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#define TRB_ENT_START 1
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#define TRB_ENT_LEN 1
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#define TRB_ISP_FIELD control /* ISP - Interrupt-on Short Packet */
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#define TRB_ISP_START 2
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#define TRB_ISP_LEN 1
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#define TRB_CH_FIELD control /* CH - Chain Bit */
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#define TRB_CH_START 4
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#define TRB_CH_LEN 1
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#define TRB_IOC_FIELD control /* IOC - Interrupt On Completion */
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#define TRB_IOC_START 5
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#define TRB_IOC_LEN 1
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#define TRB_IDT_FIELD control /* IDT - Immediate Data */
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#define TRB_IDT_START 6
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#define TRB_IDT_LEN 1
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#define TRB_DC_FIELD control /* DC - Deconfigure */
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#define TRB_DC_START 9
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#define TRB_DC_LEN 1
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#define TRB_TT_FIELD control /* TT - TRB Type */
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#define TRB_TT_START 10
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#define TRB_TT_LEN 6
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#define TRB_TRT_FIELD control /* TRT - Transfer Type */
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#define TRB_TRT_START 16
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#define TRB_TRT_LEN 2
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#define TRB_DIR_FIELD control /* DIR - Direction */
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#define TRB_DIR_START 16
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#define TRB_DIR_LEN 1
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#define TRB_EP_FIELD control /* EP - Endpoint ID */
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#define TRB_EP_START 16
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#define TRB_EP_LEN 5
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#define TRB_ID_FIELD control /* ID - Slot ID */
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#define TRB_ID_START 24
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#define TRB_ID_LEN 8
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#define TRB_MASK(tok) MASK(TRB_##tok##_START, TRB_##tok##_LEN)
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#define TRB_GET(tok, trb) (((trb)->TRB_##tok##_FIELD & TRB_MASK(tok)) \
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>> TRB_##tok##_START)
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#define TRB_SET(tok, trb, to) (trb)->TRB_##tok##_FIELD = \
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(((trb)->TRB_##tok##_FIELD & ~TRB_MASK(tok)) | \
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(((to) << TRB_##tok##_START) & TRB_MASK(tok)))
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#define TRB_DUMP(tok, trb) usb_debug(" "#tok"\t0x%04"PRIx32"\n", TRB_GET(tok, trb))
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#define TRB_CYCLE (1 << 0)
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typedef volatile struct trb {
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u32 ptr_low;
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u32 ptr_high;
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u32 status;
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u32 control;
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} trb_t;
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#define TRB_MAX_TD_SIZE 0x1F /* bits 21:17 of TD Size in TRB */
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#define EVENT_RING_SIZE 64
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typedef struct {
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trb_t *ring;
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trb_t *cur;
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trb_t *last;
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u8 ccs;
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u8 adv;
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} event_ring_t;
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/* Never raise this above 256 to prevent transfer event length overflow! */
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#define TRANSFER_RING_SIZE 32
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typedef struct {
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trb_t *ring;
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trb_t *cur;
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u8 pcs;
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} __packed transfer_ring_t;
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#define COMMAND_RING_SIZE 4
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typedef transfer_ring_t command_ring_t;
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#define SC_ROUTE_FIELD f1 /* ROUTE - Route String */
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#define SC_ROUTE_START 0
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#define SC_ROUTE_LEN 20
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#define SC_SPEED1_FIELD f1 /* SPEED - Port speed plus one (compared to usb_speed enum) */
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#define SC_SPEED1_START 20
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#define SC_SPEED1_LEN 4
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#define SC_MTT_FIELD f1 /* MTT - Multi Transaction Translator */
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#define SC_MTT_START 25
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#define SC_MTT_LEN 1
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#define SC_HUB_FIELD f1 /* HUB - Is this a hub? */
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#define SC_HUB_START 26
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#define SC_HUB_LEN 1
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#define SC_CTXENT_FIELD f1 /* CTXENT - Context Entries (number of following ep contexts) */
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#define SC_CTXENT_START 27
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#define SC_CTXENT_LEN 5
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#define SC_RHPORT_FIELD f2 /* RHPORT - Root Hub Port Number */
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#define SC_RHPORT_START 16
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#define SC_RHPORT_LEN 8
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#define SC_NPORTS_FIELD f2 /* NPORTS - Number of Ports */
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#define SC_NPORTS_START 24
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#define SC_NPORTS_LEN 8
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#define SC_TTID_FIELD f3 /* TTID - TT Hub Slot ID */
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#define SC_TTID_START 0
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#define SC_TTID_LEN 8
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#define SC_TTPORT_FIELD f3 /* TTPORT - TT Port Number */
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#define SC_TTPORT_START 8
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#define SC_TTPORT_LEN 8
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#define SC_TTT_FIELD f3 /* TTT - TT Think Time */
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#define SC_TTT_START 16
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#define SC_TTT_LEN 2
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#define SC_UADDR_FIELD f4 /* UADDR - USB Device Address */
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#define SC_UADDR_START 0
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#define SC_UADDR_LEN 8
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#define SC_STATE_FIELD f4 /* STATE - Slot State */
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#define SC_STATE_START 27
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#define SC_STATE_LEN 5
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#define SC_MASK(tok) MASK(SC_##tok##_START, SC_##tok##_LEN)
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#define SC_GET(tok, sc) (((sc)->SC_##tok##_FIELD & SC_MASK(tok)) \
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>> SC_##tok##_START)
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#define SC_SET(tok, sc, to) (sc)->SC_##tok##_FIELD = \
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(((sc)->SC_##tok##_FIELD & ~SC_MASK(tok)) | \
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(((to) << SC_##tok##_START) & SC_MASK(tok)))
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#define SC_DUMP(tok, sc) usb_debug(" "#tok"\t0x%04"PRIx32"\n", SC_GET(tok, sc))
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typedef volatile struct slotctx {
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u32 f1;
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u32 f2;
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u32 f3;
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u32 f4;
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u32 rsvd[4];
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} slotctx_t;
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#define EC_STATE_FIELD f1 /* STATE - Endpoint State */
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#define EC_STATE_START 0
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#define EC_STATE_LEN 3
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#define EC_INTVAL_FIELD f1 /* INTVAL - Interval */
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#define EC_INTVAL_START 16
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#define EC_INTVAL_LEN 8
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#define EC_CERR_FIELD f2 /* CERR - Error Count */
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#define EC_CERR_START 1
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#define EC_CERR_LEN 2
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#define EC_TYPE_FIELD f2 /* TYPE - EP Type */
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#define EC_TYPE_START 3
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#define EC_TYPE_LEN 3
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#define EC_MBS_FIELD f2 /* MBS - Max Burst Size */
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#define EC_MBS_START 8
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#define EC_MBS_LEN 8
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#define EC_MPS_FIELD f2 /* MPS - Max Packet Size */
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#define EC_MPS_START 16
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#define EC_MPS_LEN 16
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#define EC_DCS_FIELD tr_dq_low /* DCS - Dequeue Cycle State */
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#define EC_DCS_START 0
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#define EC_DCS_LEN 1
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#define EC_AVRTRB_FIELD f5 /* AVRTRB - Average TRB Length */
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#define EC_AVRTRB_START 0
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#define EC_AVRTRB_LEN 16
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#define EC_MXESIT_FIELD f5 /* MXESIT - Max ESIT Payload */
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#define EC_MXESIT_START 16
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#define EC_MXESIT_LEN 16
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#define EC_BPKTS_FIELD rsvd[0] /* BPKTS - packets tx in scheduled uframe */
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#define EC_BPKTS_START 0
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#define EC_BPKTS_LEN 6
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#define EC_BBM_FIELD rsvd[0] /* BBM - burst mode for scheduling */
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#define EC_BBM_START 11
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#define EC_BBM_LEN 1
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#define EC_MASK(tok) MASK(EC_##tok##_START, EC_##tok##_LEN)
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#define EC_GET(tok, ec) (((ec)->EC_##tok##_FIELD & EC_MASK(tok)) \
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>> EC_##tok##_START)
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#define EC_SET(tok, ec, to) (ec)->EC_##tok##_FIELD = \
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(((ec)->EC_##tok##_FIELD & ~EC_MASK(tok)) | \
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(((to) << EC_##tok##_START) & EC_MASK(tok)))
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#define EC_DUMP(tok, ec) usb_debug(" "#tok"\t0x%04"PRIx32"\n", EC_GET(tok, ec))
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enum { EP_ISOC_OUT = 1, EP_BULK_OUT = 2, EP_INTR_OUT = 3,
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EP_CONTROL = 4, EP_ISOC_IN = 5, EP_BULK_IN = 6, EP_INTR_IN = 7 };
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typedef volatile struct epctx {
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u32 f1;
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u32 f2;
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u32 tr_dq_low;
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u32 tr_dq_high;
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u32 f5;
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u32 rsvd[3];
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} epctx_t;
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#define NUM_EPS 32
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typedef union devctx {
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/* set of pointers, so we can dynamically adjust Slot/EP context size */
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struct {
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union {
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slotctx_t *slot;
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void *raw; /* Pointer to the whole dev context. */
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};
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epctx_t *ep0;
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epctx_t *eps1_30[NUM_EPS - 2];
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};
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epctx_t *ep[NUM_EPS]; /* At index 0 it's actually the slotctx,
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we have it like that so we can use
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the ep_id directly as index. */
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} devctx_t;
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typedef struct inputctx {
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union { /* The drop flags are located at the start of the */
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u32 *drop; /* structure, so a pointer to them is equivalent */
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void *raw; /* to a pointer to the whole (raw) input context. */
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};
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u32 *add;
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devctx_t dev;
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} inputctx_t;
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typedef struct intrq {
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size_t size; /* Size of each transfer */
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size_t count; /* The number of TRBs to fill at once */
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trb_t *next; /* The next TRB expected to be processed by the controller */
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trb_t *ready; /* The last TRB in the transfer ring processed by the controller */
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endpoint_t *ep;
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} intrq_t;
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typedef struct devinfo {
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devctx_t ctx;
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transfer_ring_t *transfer_rings[NUM_EPS];
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intrq_t *interrupt_queues[NUM_EPS];
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} devinfo_t;
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typedef struct erst_entry {
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u32 seg_base_lo;
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u32 seg_base_hi;
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u32 seg_size;
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u32 rsvd;
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} erst_entry_t;
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#define CAP_CAPLEN_FIELD hciparams
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#define CAP_CAPLEN_START 0
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#define CAP_CAPLEN_LEN 8
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#define CAP_CAPVER_FIELD hciparams
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#define CAP_CAPVER_START 16
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#define CAP_CAPVER_LEN 16
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#define CAP_CAPVER_HI_FIELD hciparams
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#define CAP_CAPVER_HI_START 24
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#define CAP_CAPVER_HI_LEN 8
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#define CAP_CAPVER_LO_FIELD hciparams
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#define CAP_CAPVER_LO_START 16
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#define CAP_CAPVER_LO_LEN 8
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#define CAP_MAXSLOTS_FIELD hcsparams1
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#define CAP_MAXSLOTS_START 0
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#define CAP_MAXSLOTS_LEN 7
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#define CAP_MAXINTRS_FIELD hcsparams1
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#define CAP_MAXINTRS_START 7
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#define CAP_MAXINTRS_LEN 11
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#define CAP_MAXPORTS_FIELD hcsparams1
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#define CAP_MAXPORTS_START 24
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#define CAP_MAXPORTS_LEN 8
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#define CAP_IST_FIELD hcsparams2
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#define CAP_IST_START 0
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#define CAP_IST_LEN 4
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#define CAP_ERST_MAX_FIELD hcsparams2
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#define CAP_ERST_MAX_START 4
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#define CAP_ERST_MAX_LEN 4
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#define CAP_MAX_SCRATCH_BUFS_HI_FIELD hcsparams2
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#define CAP_MAX_SCRATCH_BUFS_HI_START 21
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#define CAP_MAX_SCRATCH_BUFS_HI_LEN 5
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#define CAP_MAX_SCRATCH_BUFS_LO_FIELD hcsparams2
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#define CAP_MAX_SCRATCH_BUFS_LO_START 27
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#define CAP_MAX_SCRATCH_BUFS_LO_LEN 5
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#define CAP_U1_LATENCY_FIELD hcsparams3
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#define CAP_U1_LATENCY_START 0
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#define CAP_U1_LATENCY_LEN 8
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#define CAP_U2_LATENCY_FIELD hcsparams3
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#define CAP_U2_LATENCY_START 16
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#define CAP_U2_LATENCY_LEN 16
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#define CAP_CSZ_FIELD hccparams
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#define CAP_CSZ_START 2
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#define CAP_CSZ_LEN 1
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#define CAP_MASK(tok) MASK(CAP_##tok##_START, CAP_##tok##_LEN)
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#define CAP_GET(tok, cap) ((read32(&(cap)->CAP_##tok##_FIELD) & CAP_MASK(tok)) \
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>> CAP_##tok##_START)
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#define CTXSIZE(xhci) (CAP_GET(CSZ, (xhci)->capreg) ? 64 : 32)
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typedef struct xhci {
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struct capreg {
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u32 hciparams;
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u32 hcsparams1;
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u32 hcsparams2;
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u32 hcsparams3;
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u32 hccparams;
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u32 dboff;
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u32 rtsoff;
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} __packed *capreg;
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/* opreg is R/W is most places, so volatile access is necessary.
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volatile means that the compiler seeks byte writes if possible,
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making bitfields unusable for MMIO register blocks. Yay C :-( */
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volatile struct opreg {
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u32 usbcmd; /* 0x00 */
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#define USBCMD_RS (1 << 0)
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#define USBCMD_HCRST (1 << 1)
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#define USBCMD_INTE (1 << 2)
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u32 usbsts; /* 0x04 */
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#define USBSTS_HCH (1 << 0)
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#define USBSTS_HSE (1 << 2)
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#define USBSTS_EINT (1 << 3)
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#define USBSTS_PCD (1 << 4)
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#define USBSTS_CNR (1 << 11)
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#define USBSTS_PRSRV_MASK ((1 << 1) | 0xffffe000)
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u32 pagesize; /* 0x08 */
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u8 res1[0x13-0x0c+1]; /* 0x0C */
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u32 dnctrl; /* 0x14 */
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u32 crcr_lo; /* 0x18 */
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u32 crcr_hi; /* 0x1C */
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#define CRCR_RCS (1 << 0)
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#define CRCR_CS (1 << 1)
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#define CRCR_CA (1 << 2)
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#define CRCR_CRR (1 << 3)
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u8 res2[0x2f-0x20+1]; /* 0x20 */
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u32 dcbaap_lo; /* 0x30 */
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u32 dcbaap_hi; /* 0x34 */
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u32 config; /* 0x38 */
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#define CONFIG_LP_MASK_MaxSlotsEn 0xff
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u8 res3[0x3ff-0x3c+1]; /* 0x3C */
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struct {
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u32 portsc; /* 0x400 + 4 * port */
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#define PORTSC_CCS (1 << 0)
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#define PORTSC_PED (1 << 1)
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// BIT 2 rsvdZ
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#define PORTSC_OCA (1 << 3)
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#define PORTSC_PR (1 << 4)
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#define PORTSC_PLS (1 << 5)
|
|
#define PORTSC_PLS_MASK MASK(5, 4)
|
|
#define PORTSC_PP (1 << 9)
|
|
#define PORTSC_PORT_SPEED_START 10
|
|
#define PORTSC_PORT_SPEED (1 << PORTSC_PORT_SPEED_START)
|
|
#define PORTSC_PORT_SPEED_MASK MASK(PORTSC_PORT_SPEED_START, 4)
|
|
#define PORTSC_PIC (1 << 14)
|
|
#define PORTSC_PIC_MASK MASK(14, 2)
|
|
#define PORTSC_LWS (1 << 16)
|
|
#define PORTSC_CSC (1 << 17)
|
|
#define PORTSC_PEC (1 << 18)
|
|
#define PORTSC_WRC (1 << 19)
|
|
#define PORTSC_OCC (1 << 20)
|
|
#define PORTSC_PRC (1 << 21)
|
|
#define PORTSC_PLC (1 << 22)
|
|
#define PORTSC_CEC (1 << 23)
|
|
#define PORTSC_CAS (1 << 24)
|
|
#define PORTSC_WCE (1 << 25)
|
|
#define PORTSC_WDE (1 << 26)
|
|
#define PORTSC_WOE (1 << 27)
|
|
// BIT 29:28 rsvdZ
|
|
#define PORTSC_DR (1 << 30)
|
|
#define PORTSC_WPR (1 << 31)
|
|
#define PORTSC_RW_MASK (PORTSC_PR | PORTSC_PLS_MASK | PORTSC_PP | PORTSC_PIC_MASK | PORTSC_LWS | PORTSC_WCE | PORTSC_WDE | PORTSC_WOE)
|
|
u32 portpmsc; /* 0x404 + 4 * port */
|
|
u32 portli; /* 0x408 + 4 * port */
|
|
u32 res; /* 0x40C + 4 * port */
|
|
} __packed prs[];
|
|
} __packed *opreg;
|
|
|
|
/* R/W, volatile, MMIO -> no bitfields */
|
|
volatile struct hcrreg {
|
|
u32 mfindex;
|
|
u8 res1[0x20-0x4];
|
|
struct {
|
|
u32 iman;
|
|
u32 imod;
|
|
u32 erstsz;
|
|
u32 res;
|
|
u32 erstba_lo;
|
|
u32 erstba_hi;
|
|
u32 erdp_lo;
|
|
u32 erdp_hi;
|
|
} __packed intrrs[]; // up to 1024, but maximum host specific, given in capreg->MaxIntrs
|
|
} __packed *hcrreg;
|
|
|
|
/* R/W, volatile, MMIO -> no bitfields */
|
|
volatile u32 *dbreg;
|
|
|
|
/* R/W, volatile, Memory -> bitfields allowed */
|
|
u64 *dcbaa; /* pointers to sp_ptrs and output (device) contexts */
|
|
u64 *sp_ptrs; /* pointers to scratchpad buffers */
|
|
|
|
command_ring_t cr;
|
|
event_ring_t er;
|
|
volatile erst_entry_t *ev_ring_table;
|
|
|
|
usbdev_t *roothub;
|
|
|
|
u8 max_slots_en;
|
|
devinfo_t *dev; /* array of devinfos by slot_id */
|
|
|
|
#define DMA_SIZE (64 * 1024)
|
|
void *dma_buffer;
|
|
} xhci_t;
|
|
|
|
#define XHCI_INST(controller) ((xhci_t*)((controller)->instance))
|
|
|
|
void *xhci_align(const size_t min_align, const size_t size);
|
|
void xhci_init_cycle_ring(transfer_ring_t *, const size_t ring_size);
|
|
usbdev_t *xhci_set_address (hci_t *, usb_speed speed, int hubport, int hubaddr);
|
|
int xhci_finish_device_config(usbdev_t *);
|
|
void xhci_destroy_dev(hci_t *, int slot_id);
|
|
|
|
void xhci_reset_event_ring(event_ring_t *);
|
|
void xhci_advance_event_ring(xhci_t *);
|
|
void xhci_update_event_dq(xhci_t *);
|
|
void xhci_handle_events(xhci_t *);
|
|
int xhci_wait_for_command_aborted(xhci_t *, const trb_t *);
|
|
int xhci_wait_for_command_done(xhci_t *, const trb_t *, int clear_event);
|
|
int xhci_wait_for_transfer(xhci_t *, const int slot_id, const int ep_id);
|
|
|
|
void xhci_clear_trb(trb_t *, int pcs);
|
|
|
|
trb_t *xhci_next_command_trb(xhci_t *);
|
|
void xhci_post_command(xhci_t *);
|
|
int xhci_cmd_enable_slot(xhci_t *, int *slot_id);
|
|
int xhci_cmd_disable_slot(xhci_t *, int slot_id);
|
|
int xhci_cmd_address_device(xhci_t *, int slot_id, inputctx_t *);
|
|
int xhci_cmd_configure_endpoint(xhci_t *, int slot_id, int config_id, inputctx_t *);
|
|
int xhci_cmd_evaluate_context(xhci_t *, int slot_id, inputctx_t *);
|
|
int xhci_cmd_reset_endpoint(xhci_t *, int slot_id, int ep);
|
|
int xhci_cmd_stop_endpoint(xhci_t *, int slot_id, int ep);
|
|
int xhci_cmd_set_tr_dq(xhci_t *, int slot_id, int ep, trb_t *, int dcs);
|
|
|
|
static inline int xhci_ep_id(const endpoint_t *const ep) {
|
|
return ((ep->endpoint & 0x7f) * 2) + (ep->direction != OUT);
|
|
}
|
|
|
|
|
|
#ifdef XHCI_DUMPS
|
|
void xhci_dump_slotctx(const slotctx_t *);
|
|
void xhci_dump_epctx(const epctx_t *);
|
|
void xhci_dump_devctx(const devctx_t *, const u32 ctx_mask);
|
|
void xhci_dump_inputctx(const inputctx_t *);
|
|
void xhci_dump_transfer_trb(const trb_t *);
|
|
void xhci_dump_transfer_trbs(const trb_t *first, const trb_t *last);
|
|
#else
|
|
#define xhci_dump_slotctx(args...) do {} while(0)
|
|
#define xhci_dump_epctx(args...) do {} while(0)
|
|
#define xhci_dump_devctx(args...) do {} while(0)
|
|
#define xhci_dump_inputctx(args...) do {} while(0)
|
|
#define xhci_dump_transfer_trb(args...) do {} while(0)
|
|
#define xhci_dump_transfer_trbs(args...) do {} while(0)
|
|
#endif
|
|
|
|
#endif
|