02a1b338f8
A UPD HybridStorageMode allows a platform to dynamically configure the PCIe strap configuration required if an Optane device is connected. The strap configuration is done by HECI commands between FSP and CSE to override the default PCIe strap value, and the updated strap value is stored in SPI RW data to be used on the next boot. CSE Lite supports the strap override when running on CSE RW partition, while CSE RO partition does not support it because CSE RO is not allowed to access SPI RW data. The strap override failure on CSE RO causes FSP not initializing PCH Clkreq and PCIe port mapping and this results NVMe and Optane initialization failure. By disabling HybridStorageMode in case of CSE RO boot, NVMe detection is done by the default PCIe configuration and Optane is detected as a single NVMe storage device on CSE RO boot in recovery mode. Both NVMe and Optane devices detection as well as OS installation to these storage devices are verified on CSE RO boot in recovery mode. BUG=b:158643194 TEST=boot and verified with tglrvp and volteer in recovery mode Cq-Depend: chrome-internal:3100721 Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com> Change-Id: I5397cfc007069debe3701bf1e38e81bd17a29f0c Reviewed-on: https://review.coreboot.org/c/coreboot/+/42282 Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> |
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| Documentation | ||
| LICENSES | ||
| configs | ||
| payloads | ||
| src | ||
| tests | ||
| util | ||
| .checkpatch.conf | ||
| .clang-format | ||
| .editorconfig | ||
| .gitignore | ||
| .gitmodules | ||
| .gitreview | ||
| AUTHORS | ||
| COPYING | ||
| MAINTAINERS | ||
| Makefile | ||
| Makefile.inc | ||
| README.md | ||
| gnat.adc | ||
| toolchain.inc | ||
README.md
coreboot README
coreboot is a Free Software project aimed at replacing the proprietary BIOS (firmware) found in most computers. coreboot performs a little bit of hardware initialization and then executes additional boot logic, called a payload.
With the separation of hardware initialization and later boot logic, coreboot can scale from specialized applications that run directly firmware, run operating systems in flash, load custom bootloaders, or implement firmware standards, like PC BIOS services or UEFI. This allows for systems to only include the features necessary in the target application, reducing the amount of code and flash space required.
coreboot was formerly known as LinuxBIOS.
Payloads
After the basic initialization of the hardware has been performed, any desired "payload" can be started by coreboot.
See https://www.coreboot.org/Payloads for a list of supported payloads.
Supported Hardware
coreboot supports a wide range of chipsets, devices, and mainboards.
For details please consult:
Build Requirements
- make
- gcc / g++
Because Linux distribution compilers tend to use lots of patches. coreboot
does lots of "unusual" things in its build system, some of which break due
to those patches, sometimes by gcc aborting, sometimes - and that's worse -
by generating broken object code.
Two options: use our toolchain (eg. make crosstools-i386) or enable the
ANY_TOOLCHAINKconfig option if you're feeling lucky (no support in this case). - iasl (for targets with ACPI support)
- pkg-config
- libssl-dev (openssl)
Optional:
- doxygen (for generating/viewing documentation)
- gdb (for better debugging facilities on some targets)
- ncurses (for
make menuconfigandmake nconfig) - flex and bison (for regenerating parsers)
Building coreboot
Please consult https://www.coreboot.org/Build_HOWTO for details.
Testing coreboot Without Modifying Your Hardware
If you want to test coreboot without any risks before you really decide to use it on your hardware, you can use the QEMU system emulator to run coreboot virtually in QEMU.
Please see https://www.coreboot.org/QEMU for details.
Website and Mailing List
Further details on the project, a FAQ, many HOWTOs, news, development guidelines and more can be found on the coreboot website:
You can contact us directly on the coreboot mailing list:
https://www.coreboot.org/Mailinglist
Copyright and License
The copyright on coreboot is owned by quite a large number of individual developers and companies. Please check the individual source files for details.
coreboot is licensed under the terms of the GNU General Public License (GPL). Some files are licensed under the "GPL (version 2, or any later version)", and some files are licensed under the "GPL, version 2". For some parts, which were derived from other projects, other (GPL-compatible) licenses may apply. Please check the individual source files for details.
This makes the resulting coreboot images licensed under the GPL, version 2.