a1e46aea79
The following was tested: - Using two DDR2 DIMMs - S3 sleep and resume (on SeaBIOS it needs sercon disabled) - Ethernet NIC - Libgfxinit (native res and textmode) - SATA - USB - 800MHz FSB CPU (Pentium(R) E5200 @ 2.50GHz) - PS2 Keyboard - Serial output TODO: - Add ACPI code for SuperIO devices (done in a follow-up patch) - Add documentation TESTED with SeaBIOS (sercon disabled), Linux 4.19 Change-Id: I483e1143e4095b8a58fed142d31ca7f233a854e2 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/30239 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
109 lines
3.3 KiB
Text
109 lines
3.3 KiB
Text
#
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# This file is part of the coreboot project.
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#
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# Copyright (C) 2017 Arthur Heymans <arthur@aheymans.xyz>
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#
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# This program is free software; you can redistribute it and/or modify
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# it under the terms of the GNU General Public License as published by
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# the Free Software Foundation; either version 2 of the License, or
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# (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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chip northbridge/intel/x4x # Northbridge
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device cpu_cluster 0 on # APIC cluster
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chip cpu/intel/socket_LGA775
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device lapic 0 on end
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end
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chip cpu/intel/model_1067x # CPU
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device lapic 0xACAC off end
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end
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end
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device domain 0 on # PCI domain
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subsystemid 0x17aa 0x304f inherit
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device pci 0.0 on end # Host Bridge
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device pci 1.0 on end # PEG
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device pci 2.0 on end # Integrated graphics controller
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chip southbridge/intel/i82801gx # Southbridge
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register "pirqa_routing" = "0x0b"
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register "pirqb_routing" = "0x0b"
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register "pirqc_routing" = "0x0b"
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register "pirqd_routing" = "0x0b"
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register "pirqe_routing" = "0x80"
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register "pirqf_routing" = "0x80"
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register "pirqg_routing" = "0x80"
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register "pirqh_routing" = "0x0b"
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# GPI routing
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# 0 No effect (default)
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# 1 SMI# (if corresponding ALT_GPI_SMI_EN bit is also set)
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# 2 SCI (if corresponding GPIO_EN bit is also set)
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register "gpi13_routing" = "1" # ??vendor
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register "ide_enable_primary" = "0x1"
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register "sata_ahci" = "0x0" # AHCI not supported on this ICH7 variant
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register "gpe0_en" = "0x440"
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device pci 1b.0 on end # Audio
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device pci 1c.0 on end # PCIe 1
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device pci 1c.1 on # PCIe 2: NIC
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device pci 00.0 on
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end
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end
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device pci 1c.2 off end # PCIe 3
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device pci 1c.3 off end # PCIe 4
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device pci 1c.4 off end # PCIe 5
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device pci 1c.5 off end # PCIe 6
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device pci 1d.0 on end # USB
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device pci 1d.1 on end # USB
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device pci 1d.2 on end # USB
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device pci 1d.3 on end # USB
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device pci 1d.7 on end # USB
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device pci 1e.0 on end # PCI bridge
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device pci 1e.2 off end # AC'97 Audio Controller
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device pci 1e.3 off end # AC'97 Modem Controller
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device pci 1f.0 on # LPC bridge
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chip superio/smsc/smscsuperio
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device pnp 2e.0 off end # Floppy
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device pnp 2e.3 on # Parallel Port
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io 0x60 = 0x378
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irq 0x70 = 7
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drq 0x74 = 3
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end
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device pnp 2e.4 on # COM1
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io 0x60 = 0x3f8
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irq 0x70 = 4
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end
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device pnp 2e.5 off end # COM2
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device pnp 2e.7 on # Keyboard
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io 0x60 = 0x60 # Can't read this back
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io 0x62 = 0x64 # Can't read this back
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irq 0x70 = 1
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irq 0x72 = 12
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end
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device pnp 2e.a on # Runtime Regs
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io 0x60 = 0x0a00
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end
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end # smscsuperio
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end
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device pci 1f.1 on end # PATA/IDE
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device pci 1f.2 on end # SATA
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device pci 1f.3 on # SMbus
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chip drivers/i2c/at24rf08c
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device i2c 54 on end
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device i2c 55 on end
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device i2c 56 on end
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device i2c 57 on end
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end
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chip drivers/i2c/ck505
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register "mask" = "{ 0x00, 0x80 }"
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register "regs" = "{ 0x00, 0x80 }"
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device i2c 69 on end
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end
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end
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end
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end
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end
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