a20ac2f7b3
This continues what was done in commit a73b93157f
(tree: drop last paragraph of GPL copyright header)
Change-Id: Ifb8d2d13f7787657445817bdde8dc15df375e173
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12914
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
131 lines
3.5 KiB
C
131 lines
3.5 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2011 The Chromium OS Authors. All rights reserved.
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* Copyright (C) 2013 Sage Electronic Engineering, LLC.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <stdint.h>
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#include <string.h>
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#include <arch/io.h>
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#include "pch.h"
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#include "gpio.h"
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#define MAX_GPIO_NUMBER 75 /* zero based */
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static const int gpio_reg_offsets[] = {GP_LVL, GP_LVL2, GP_LVL3};
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void setup_pch_gpios(const struct pch_gpio_map *gpio)
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{
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u16 gpiobase = pci_read_config16(PCH_LPC_DEV, GPIO_BASE) & 0xfffc;
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/* GPIO Set 1 */
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if (gpio->set1.level)
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outl(*((u32*)gpio->set1.level), gpiobase + GP_LVL);
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if (gpio->set1.mode)
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outl(*((u32*)gpio->set1.mode), gpiobase + GPIO_USE_SEL);
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if (gpio->set1.direction)
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outl(*((u32*)gpio->set1.direction), gpiobase + GP_IO_SEL);
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if (gpio->set1.reset)
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outl(*((u32*)gpio->set1.reset), gpiobase + GP_RST_SEL1);
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if (gpio->set1.invert)
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outl(*((u32*)gpio->set1.invert), gpiobase + GPI_INV);
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if (gpio->set1.blink)
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outl(*((u32*)gpio->set1.blink), gpiobase + GPO_BLINK);
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/* GPIO Set 2 */
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if (gpio->set2.level)
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outl(*((u32*)gpio->set2.level), gpiobase + GP_LVL2);
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if (gpio->set2.mode)
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outl(*((u32*)gpio->set2.mode), gpiobase + GPIO_USE_SEL2);
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if (gpio->set2.direction)
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outl(*((u32*)gpio->set2.direction), gpiobase + GP_IO_SEL2);
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if (gpio->set2.reset)
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outl(*((u32*)gpio->set2.reset), gpiobase + GP_RST_SEL2);
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/* GPIO Set 3 */
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if (gpio->set3.level)
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outl(*((u32*)gpio->set3.level), gpiobase + GP_LVL3);
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if (gpio->set3.mode)
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outl(*((u32*)gpio->set3.mode), gpiobase + GPIO_USE_SEL3);
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if (gpio->set3.direction)
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outl(*((u32*)gpio->set3.direction), gpiobase + GP_IO_SEL3);
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if (gpio->set3.reset)
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outl(*((u32*)gpio->set3.reset), gpiobase + GP_RST_SEL3);
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}
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int get_gpio(int gpio_num)
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{
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u16 gpio_base = pci_read_config16(PCH_LPC_DEV, GPIO_BASE) & 0xfffc;
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int index, bit;
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if (gpio_num > MAX_GPIO_NUMBER)
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return 0; /* Just ignore wrong gpio numbers. */
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index = gpio_num / 32;
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bit = gpio_num % 32;
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return (inl(gpio_base + gpio_reg_offsets[index]) >> bit) & 1;
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}
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void set_gpio(int gpio_num)
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{
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u16 gpio_base = pci_read_config16(PCH_LPC_DEV, GPIO_BASE) & 0xfffc;
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u32 index, bit, level;
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if (gpio_num <= MAX_GPIO_NUMBER){
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index = gpio_num / 32;
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bit = gpio_num % 32;
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level = inl(gpio_base + gpio_reg_offsets[index]);
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outl((gpio_base + gpio_reg_offsets[index]), level | (1UL << bit));
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}
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return;
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}
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void clear_gpio(int gpio_num)
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{
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u16 gpio_base = pci_read_config16(PCH_LPC_DEV, GPIO_BASE) & 0xfffc;
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u32 index, bit, level;
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if (gpio_num <= MAX_GPIO_NUMBER){
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index = gpio_num / 32;
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bit = gpio_num % 32;
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level = inl(gpio_base + gpio_reg_offsets[index]);
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outl((gpio_base + gpio_reg_offsets[index]), level & (~(1UL << bit)));
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}
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return;
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}
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/*
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* get a number comprised of multiple GPIO values. gpio_num_array points to
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* the array of gpio pin numbers to scan, terminated by -1.
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*/
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unsigned get_gpios(const int *gpio_num_array)
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{
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int gpio;
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unsigned bitmask = 1;
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unsigned vector = 0;
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while (bitmask &&
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((gpio = *gpio_num_array++) != -1)) {
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if (get_gpio(gpio))
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vector |= bitmask;
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bitmask <<= 1;
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}
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return vector;
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}
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