7a9520483a
https://ark.intel.com/products/71620/Intel-NUC-Board-DCP847SKE Created using autoport and manual edits. mainboard_fill_pei_data copied and adjusted from samsung/lumpy. Tested: - RAM slots with 2x4GB Kingston KVR1333D3S9/4G (DDR3-1333 1.5V). - RAM slots with 2x4GB Kingston KVR16LS11/4G (DDR3L-1600 1.35V). - SeaBIOS stable payload. - Linux 4.13.14 payload. - Booting into Linux 4.13.14 with Debian/unstable installed on the internal mSATA slot. - Non-native raminit (works). - Native raminit - KVR1333D3S9 doesn't work. - KVR16LS11 only works at 1.5V. - Native VGA init, HDMI port detection with libgfxinit. - Basic ACPI functions (power button event; power-off; reboot). - Suspend to RAM and resume works. - PCIe WLAN in half-minicard slot. - USB device in half-minicard slot. - PCIe device in full-minicard slot. - mSATA device in full-minicard slot. - Fan spins up/down in response to CPU load. Known issues: - Native raminit fails timC calibration with the RAM I have. - Technical Product Specification mentions overcurrent protection for back panel and front panel USB connectors, but I haven't been able to trigger it with either native fw or coreboot (tried up to 2.5A load). Untested: - USB debug port. Change-Id: I6e210310f55c051eaf61e0698fed855eda5d7d90 Signed-off-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de> Reviewed-on: https://review.coreboot.org/22683 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
209 lines
5.6 KiB
C
209 lines
5.6 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2008-2009 coresystems GmbH
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* Copyright (C) 2014 Vladimir Serbinenko
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; version 2 of
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* the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <southbridge/intel/common/gpio.h>
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static const struct pch_gpio_set1 pch_gpio_set1_mode = {
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.gpio0 = GPIO_MODE_NATIVE,
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.gpio1 = GPIO_MODE_GPIO,
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.gpio2 = GPIO_MODE_GPIO,
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.gpio3 = GPIO_MODE_GPIO,
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.gpio4 = GPIO_MODE_GPIO,
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.gpio5 = GPIO_MODE_NATIVE,
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.gpio6 = GPIO_MODE_GPIO,
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.gpio7 = GPIO_MODE_GPIO,
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.gpio8 = GPIO_MODE_GPIO,
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.gpio9 = GPIO_MODE_NATIVE,
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.gpio10 = GPIO_MODE_NATIVE,
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.gpio11 = GPIO_MODE_NATIVE,
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.gpio12 = GPIO_MODE_NATIVE,
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.gpio13 = GPIO_MODE_NATIVE,
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.gpio14 = GPIO_MODE_NATIVE,
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.gpio15 = GPIO_MODE_GPIO,
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.gpio16 = GPIO_MODE_NATIVE,
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.gpio17 = GPIO_MODE_GPIO,
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.gpio18 = GPIO_MODE_NATIVE,
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.gpio19 = GPIO_MODE_NATIVE,
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.gpio20 = GPIO_MODE_GPIO,
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.gpio21 = GPIO_MODE_NATIVE,
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.gpio22 = GPIO_MODE_GPIO,
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.gpio23 = GPIO_MODE_NATIVE,
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.gpio24 = GPIO_MODE_GPIO,
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.gpio25 = GPIO_MODE_NATIVE,
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.gpio26 = GPIO_MODE_NATIVE,
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.gpio27 = GPIO_MODE_GPIO,
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.gpio28 = GPIO_MODE_GPIO,
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.gpio29 = GPIO_MODE_GPIO,
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.gpio30 = GPIO_MODE_NATIVE,
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.gpio31 = GPIO_MODE_NATIVE,
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};
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static const struct pch_gpio_set1 pch_gpio_set1_direction = {
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.gpio1 = GPIO_DIR_INPUT,
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.gpio2 = GPIO_DIR_INPUT,
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.gpio3 = GPIO_DIR_INPUT,
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.gpio4 = GPIO_DIR_INPUT,
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.gpio6 = GPIO_DIR_INPUT,
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.gpio7 = GPIO_DIR_INPUT,
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.gpio8 = GPIO_DIR_OUTPUT,
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.gpio15 = GPIO_DIR_OUTPUT,
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.gpio17 = GPIO_DIR_INPUT,
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.gpio20 = GPIO_DIR_INPUT,
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.gpio22 = GPIO_DIR_INPUT, /* BIOS jumper: 1 = normal, 0 = setup */
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.gpio24 = GPIO_DIR_OUTPUT,
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.gpio27 = GPIO_DIR_OUTPUT,
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.gpio28 = GPIO_DIR_OUTPUT,
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.gpio29 = GPIO_DIR_OUTPUT,
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};
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/*
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* GPIO8: RAM voltage: LOW: 1.5V, HIGH: 1.35V
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* GPIO27: Set to HIGH on S3/S4/S5 by original fw dsdt.
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* GPIO29: Actually NATIVE? Can't clear, stays 1.
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* SLP_LAN# is affected by soft-strap according to docs.
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* Others: No visible effect when toggling.
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*/
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static const struct pch_gpio_set1 pch_gpio_set1_level = {
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.gpio8 = GPIO_LEVEL_LOW,
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.gpio15 = GPIO_LEVEL_HIGH,
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.gpio24 = GPIO_LEVEL_HIGH,
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.gpio27 = GPIO_LEVEL_LOW,
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.gpio28 = GPIO_LEVEL_HIGH,
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.gpio29 = GPIO_LEVEL_HIGH,
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};
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static const struct pch_gpio_set1 pch_gpio_set1_reset = {
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.gpio30 = GPIO_RESET_RSMRST,
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};
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static const struct pch_gpio_set1 pch_gpio_set1_invert = {
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};
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static const struct pch_gpio_set1 pch_gpio_set1_blink = {
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};
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static const struct pch_gpio_set2 pch_gpio_set2_mode = {
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.gpio32 = GPIO_MODE_NATIVE,
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.gpio33 = GPIO_MODE_NATIVE,
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.gpio34 = GPIO_MODE_GPIO,
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.gpio35 = GPIO_MODE_GPIO,
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.gpio36 = GPIO_MODE_GPIO,
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.gpio37 = GPIO_MODE_GPIO,
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.gpio38 = GPIO_MODE_GPIO,
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.gpio39 = GPIO_MODE_GPIO,
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.gpio40 = GPIO_MODE_NATIVE,
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.gpio41 = GPIO_MODE_NATIVE,
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.gpio42 = GPIO_MODE_NATIVE,
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.gpio43 = GPIO_MODE_NATIVE,
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.gpio44 = GPIO_MODE_NATIVE,
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.gpio45 = GPIO_MODE_NATIVE,
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.gpio46 = GPIO_MODE_NATIVE,
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.gpio47 = GPIO_MODE_NATIVE,
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.gpio48 = GPIO_MODE_GPIO,
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.gpio49 = GPIO_MODE_GPIO,
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.gpio50 = GPIO_MODE_NATIVE,
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.gpio51 = GPIO_MODE_NATIVE,
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.gpio52 = GPIO_MODE_NATIVE,
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.gpio53 = GPIO_MODE_GPIO,
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.gpio54 = GPIO_MODE_NATIVE,
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.gpio55 = GPIO_MODE_GPIO,
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.gpio56 = GPIO_MODE_NATIVE,
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.gpio57 = GPIO_MODE_GPIO,
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.gpio58 = GPIO_MODE_NATIVE,
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.gpio59 = GPIO_MODE_NATIVE,
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.gpio60 = GPIO_MODE_NATIVE,
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.gpio61 = GPIO_MODE_NATIVE,
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.gpio62 = GPIO_MODE_NATIVE,
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.gpio63 = GPIO_MODE_NATIVE,
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};
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static const struct pch_gpio_set2 pch_gpio_set2_direction = {
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.gpio34 = GPIO_DIR_OUTPUT,
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.gpio35 = GPIO_DIR_INPUT, /* mSATA presence detect */
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.gpio36 = GPIO_DIR_INPUT,
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.gpio37 = GPIO_DIR_OUTPUT,
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.gpio38 = GPIO_DIR_INPUT,
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.gpio39 = GPIO_DIR_INPUT,
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.gpio48 = GPIO_DIR_INPUT,
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.gpio49 = GPIO_DIR_INPUT,
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.gpio53 = GPIO_DIR_OUTPUT,
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.gpio55 = GPIO_DIR_OUTPUT,
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.gpio57 = GPIO_DIR_INPUT,
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};
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static const struct pch_gpio_set2 pch_gpio_set2_level = {
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.gpio34 = GPIO_LEVEL_LOW,
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.gpio37 = GPIO_LEVEL_LOW,
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.gpio53 = GPIO_LEVEL_HIGH,
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.gpio55 = GPIO_LEVEL_LOW,
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};
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static const struct pch_gpio_set2 pch_gpio_set2_reset = {
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};
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static const struct pch_gpio_set3 pch_gpio_set3_mode = {
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.gpio64 = GPIO_MODE_NATIVE,
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.gpio65 = GPIO_MODE_NATIVE,
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.gpio66 = GPIO_MODE_GPIO,
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.gpio67 = GPIO_MODE_GPIO,
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.gpio68 = GPIO_MODE_GPIO,
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.gpio69 = GPIO_MODE_GPIO,
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.gpio70 = GPIO_MODE_NATIVE,
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.gpio71 = GPIO_MODE_NATIVE,
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.gpio72 = GPIO_MODE_NATIVE,
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.gpio73 = GPIO_MODE_NATIVE,
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.gpio74 = GPIO_MODE_NATIVE,
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.gpio75 = GPIO_MODE_NATIVE,
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};
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static const struct pch_gpio_set3 pch_gpio_set3_direction = {
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.gpio66 = GPIO_DIR_OUTPUT,
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.gpio67 = GPIO_DIR_INPUT,
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.gpio68 = GPIO_DIR_OUTPUT,
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.gpio69 = GPIO_DIR_INPUT,
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};
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static const struct pch_gpio_set3 pch_gpio_set3_level = {
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.gpio66 = GPIO_LEVEL_LOW,
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.gpio68 = GPIO_LEVEL_HIGH,
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};
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static const struct pch_gpio_set3 pch_gpio_set3_reset = {
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};
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const struct pch_gpio_map mainboard_gpio_map = {
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.set1 = {
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.mode = &pch_gpio_set1_mode,
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.direction = &pch_gpio_set1_direction,
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.level = &pch_gpio_set1_level,
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.blink = &pch_gpio_set1_blink,
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.invert = &pch_gpio_set1_invert,
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.reset = &pch_gpio_set1_reset,
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},
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.set2 = {
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.mode = &pch_gpio_set2_mode,
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.direction = &pch_gpio_set2_direction,
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.level = &pch_gpio_set2_level,
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.reset = &pch_gpio_set2_reset,
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},
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.set3 = {
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.mode = &pch_gpio_set3_mode,
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.direction = &pch_gpio_set3_direction,
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.level = &pch_gpio_set3_level,
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.reset = &pch_gpio_set3_reset,
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},
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};
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