faf7a8e859
The Harcuvar CRB is a reference platform of Intel Atom C3000 SoC
("Denverton" and "Denverton-NS") for the communications segment/market.
The MohonPeak coreboot was used as the starting template with
additions/modifications from other Intel Apollo Lake/Skylake coreboot.
Tested with TianoCore payload (UDK2015) and Poky (Yocto
Project Reference Distro) 2.0 with kernel 4.1.8 booted from
SATA drive and external USB pendrive.
Change-Id: I088833e36e2d22d1fe1610b8dca1454092da511a
Signed-off-by: Mariusz Szafranski <mariuszx.szafranski@intel.com>
Reviewed-on: https://review.coreboot.org/20862
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: FEI WANG <wangfei.jimei@gmail.com>
74 lines
2.8 KiB
Text
74 lines
2.8 KiB
Text
##
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## This file is part of the coreboot project.
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##
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## Copyright (C) 2014 - 2017 Intel Corporation.
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##
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## This program is free software; you can redistribute it and/or modify
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## it under the terms of the GNU General Public License as published by
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## the Free Software Foundation; version 2 of the License.
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##
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## This program is distributed in the hope that it will be useful,
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## but WITHOUT ANY WARRANTY; without even the implied warranty of
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## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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## GNU General Public License for more details.
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##
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chip soc/intel/denverton_ns
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# configure pirq routing
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register "pirqa_routing" = "11"
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register "pirqb_routing" = "10"
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register "pirqc_routing" = "06"
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register "pirqd_routing" = "07"
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register "pirqe_routing" = "12"
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register "pirqf_routing" = "14"
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register "pirqg_routing" = "15"
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register "pirqh_routing" = "15"
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# configure device interrupt routing
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register "ir00_routing" = "0x3217" # IR00, Dev31
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register "ir01_routing" = "0x3210" # IR01, Dev22
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register "ir02_routing" = "0x3211" # IR02, Dev23
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register "ir03_routing" = "0x3217" # IR03, Dev5
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register "ir04_routing" = "0x3212" # IR04, Dev6
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register "ir05_routing" = "0x3210" # IR05, Dev24
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register "ir06_routing" = "0x3214" # IR06, Dev19
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register "ir07_routing" = "0x3210" # IR07, Dev9/10/11/12
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register "ir08_routing" = "0x7654" # IR08, Dev14/15/16/17
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register "ir09_routing" = "0x3213" # IR09, Dev21
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register "ir10_routing" = "0x3210" # IR10, Dev26/18
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register "ir11_routing" = "0x3215" # IR11, Dev20
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register "ir12_routing" = "0x3210" # IR12, Dev27
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# configure interrupt polarity control
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register "ipc0" = "0x00ff4000" # IPC0, PIRQA-H (IRQ16-23) should always be ActiveLow
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register "ipc1" = "0x00000000" # IPC1
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register "ipc2" = "0x00000000" # IPC2
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register "ipc3" = "0x00000000" # IPC3
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device cpu_cluster 0 on
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device lapic 0 on end
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end
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device domain 0 on
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device pci 00.0 on end # Host Bridge
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device pci 04.0 on end # RAS
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device pci 05.0 on end # RCEC(Root Complex Event Collector)
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device pci 06.0 on end # Virtual root port 2 (QAT)
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device pci 09.0 on end # PCI Express Port 0, cluster #0, x8
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device pci 0e.0 on end # PCI Express Port 4, cluster #1, x4
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device pci 10.0 on end # PCI Express Port 6, cluster #1, x4
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device pci 12.0 on end # SMBus Controller 1
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device pci 14.0 on end # SATA Controller 1
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device pci 15.0 on end # XHCI USB Controller
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device pci 16.0 on end # Virtual root port 0 (10GBE0)
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device pci 17.0 on end # Virtual root port 1 (10GBE1)
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device pci 18.0 on end # CSME HECI 1
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device pci 1a.0 on end # UART 0
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device pci 1a.1 on end # UART 1
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device pci 1a.2 on end # UART 2
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device pci 1c.0 on end # eMMC
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device pci 1f.0 on end # LPC bridge
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device pci 1f.2 on end # PMC/ACPI
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device pci 1f.4 on end # SMBus Controller 0
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device pci 1f.5 on end # SPI Controller
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end
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end
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