coreboot-kgpe-d16/src/soc/intel/Kconfig
Nico Huber a0e72c4867 fsp2_0: Gather Kconfig declarations
Move more Kconfig declarations to drivers/intel/fsp2_0/ and document
them properly. This way, we don't have to repeat dependencies and have
the prompts in a common place. We can also easily hide the prompt for
the header path in case the FSP repository is used.

SP platforms were skipped as their Kconfig is too weird but they
shouldn't hold other platforms back.

Change-Id: Iba5af49bcd15427e9eb9b111e6c4cc9bcb7adcae
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40125
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by:  Felix Singer <felixsinger@posteo.net>
2020-04-05 23:26:24 +00:00

40 lines
1.3 KiB
Text

# Load all chipsets
source "src/soc/intel/*/Kconfig"
# Load common config
source "src/soc/intel/common/Kconfig.common"
config INTEL_HAS_TOP_SWAP
bool
help
Set this config if the Intel SoC supports top swap feature
config INTEL_ADD_TOP_SWAP_BOOTBLOCK
bool "Include a Top swap bootblock"
default n
depends on INTEL_HAS_TOP_SWAP
help
Intel PCH/Southbridges have feature that it is possible to have
the southbridge/PCH look for the bootblock at a 64K or
128K/256K/512K/1MB (in case of newer SoCs) offset
instead of the usual top of flash.
Select this to put a 'second' bootblock.
config INTEL_TOP_SWAP_BOOTBLOCK_SIZE
hex "Size of top swap boot block"
depends on INTEL_ADD_TOP_SWAP_BOOTBLOCK
default 0x10000
help
Set this config to a supported topswap size.
Valid sizes: 0x10000 0x20000 0x40000 0x80000 0x100000
config INTEL_TOP_SWAP_FIT_ENTRY_FMAP_REG
string
depends on INTEL_ADD_TOP_SWAP_BOOTBLOCK
help
Use this config to specify the name of a FMAP region (which should
hold a microcode) whose address as the first entry in the topswap FIT.
This is useful in creating a asymmetric FIT in top swap bootblock
than the one in non-topswap bootblock. This string will be passed
onto ifittool (-A -n option). ifittool will not parse the region for MCU
entries, and only locate the region and insert its address into FIT.