83abd81c8a
This patch adds CC6 power save support to the AMD Family 15h support code. As CC6 is a complex power saving state that relies heavily on CPU, northbridge, and southbridge cooperation, this patch alters significant amounts of code throughout the tree simultaneously. Allowing the CPU to enter CC6 allows the second level of turbo boost to be reached, and also provides significant power savings when the system is idle due to the complete core shutdown. Change-Id: I44ce157cda97fb85f3e8f3d7262d4712b5410670 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/11979 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
161 lines
4.7 KiB
C
161 lines
4.7 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2010 Advanced Micro Devices, Inc.
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* Copyright (C) 2015 Raptor Engineering
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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/*
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* ACPI - create the Fixed ACPI Description Tables (FADT)
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*/
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#include <string.h>
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#include <console/console.h>
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#include <arch/acpi.h>
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#include <arch/io.h>
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#include <device/device.h>
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#include <cpu/amd/powernow.h>
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#include "sb800.h"
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void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt)
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{
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acpi_header_t *header = &(fadt->header);
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printk(BIOS_DEBUG, "pm_base: 0x%04x\n", SB800_ACPI_IO_BASE);
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/* Prepare the header */
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memset((void *)fadt, 0, sizeof(acpi_fadt_t));
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memcpy(header->signature, "FACP", 4);
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header->length = 244;
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header->revision = 3;
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memcpy(header->oem_id, OEM_ID, 6);
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memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8);
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memcpy(header->asl_compiler_id, ASLC, 4);
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header->asl_compiler_revision = 0;
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fadt->firmware_ctrl = (u32) facs;
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fadt->dsdt = (u32) dsdt;
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/* 3=Workstation,4=Enterprise Server, 7=Performance Server */
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fadt->preferred_pm_profile = 0x03;
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fadt->sci_int = 9;
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/* disable system management mode by setting to 0: */
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fadt->smi_cmd = 0;
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fadt->acpi_enable = 0xf0;
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fadt->acpi_disable = 0xf1;
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fadt->s4bios_req = 0x0;
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fadt->pstate_cnt = 0xe2;
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fadt->pm1a_evt_blk = ACPI_PM_EVT_BLK;
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fadt->pm1b_evt_blk = 0x0000;
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fadt->pm1a_cnt_blk = ACPI_PM1_CNT_BLK;
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fadt->pm1b_cnt_blk = 0x0000;
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fadt->pm2_cnt_blk = ACPI_PMA_CNT_BLK;
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fadt->pm_tmr_blk = ACPI_PM_TMR_BLK;
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fadt->gpe0_blk = ACPI_GPE0_BLK;
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fadt->gpe1_blk = 0x0000; /* we don't have gpe1 block, do we? */
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fadt->pm1_evt_len = 4;
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fadt->pm1_cnt_len = 2;
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fadt->pm2_cnt_len = 1;
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fadt->pm_tmr_len = 4;
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fadt->gpe0_blk_len = 8;
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fadt->gpe1_blk_len = 0;
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fadt->gpe1_base = 0;
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fadt->cst_cnt = 0xe3;
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fadt->p_lvl2_lat = 101;
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fadt->p_lvl3_lat = 1001;
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fadt->flush_size = 0;
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fadt->flush_stride = 0;
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fadt->duty_offset = 1;
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fadt->duty_width = 3;
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fadt->day_alrm = 0; /* 0x7d these have to be */
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fadt->mon_alrm = 0; /* 0x7e added to cmos.layout */
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fadt->century = 0; /* 0x7f to make rtc alarm work */
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fadt->iapc_boot_arch = 0x3; /* See table 5-11 */
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fadt->flags = 0x0001c1a5;/* 0x25; */
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fadt->res2 = 0;
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fadt->reset_reg.space_id = 1;
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fadt->reset_reg.bit_width = 8;
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fadt->reset_reg.bit_offset = 0;
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fadt->reset_reg.resv = 0;
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fadt->reset_reg.addrl = 0xcf9;
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fadt->reset_reg.addrh = 0x0;
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fadt->reset_value = 6;
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fadt->x_firmware_ctl_l = (u32) facs;
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fadt->x_firmware_ctl_h = 0;
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fadt->x_dsdt_l = (u32) dsdt;
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fadt->x_dsdt_h = 0;
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fadt->x_pm1a_evt_blk.space_id = 1;
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fadt->x_pm1a_evt_blk.bit_width = 32;
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fadt->x_pm1a_evt_blk.bit_offset = 0;
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fadt->x_pm1a_evt_blk.resv = 0;
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fadt->x_pm1a_evt_blk.addrl = ACPI_PM_EVT_BLK;
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fadt->x_pm1a_evt_blk.addrh = 0x0;
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fadt->x_pm1b_evt_blk.space_id = 1;
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fadt->x_pm1b_evt_blk.bit_width = 4;
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fadt->x_pm1b_evt_blk.bit_offset = 0;
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fadt->x_pm1b_evt_blk.resv = 0;
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fadt->x_pm1b_evt_blk.addrl = 0x0;
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fadt->x_pm1b_evt_blk.addrh = 0x0;
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fadt->x_pm1a_cnt_blk.space_id = 1;
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fadt->x_pm1a_cnt_blk.bit_width = 16;
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fadt->x_pm1a_cnt_blk.bit_offset = 0;
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fadt->x_pm1a_cnt_blk.resv = 0;
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fadt->x_pm1a_cnt_blk.addrl = ACPI_PM1_CNT_BLK;
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fadt->x_pm1a_cnt_blk.addrh = 0x0;
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fadt->x_pm1b_cnt_blk.space_id = 1;
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fadt->x_pm1b_cnt_blk.bit_width = 2;
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fadt->x_pm1b_cnt_blk.bit_offset = 0;
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fadt->x_pm1b_cnt_blk.resv = 0;
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fadt->x_pm1b_cnt_blk.addrl = 0x0;
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fadt->x_pm1b_cnt_blk.addrh = 0x0;
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fadt->x_pm2_cnt_blk.space_id = 1;
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fadt->x_pm2_cnt_blk.bit_width = 0;
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fadt->x_pm2_cnt_blk.bit_offset = 0;
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fadt->x_pm2_cnt_blk.resv = 0;
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fadt->x_pm2_cnt_blk.addrl = ACPI_PMA_CNT_BLK;
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fadt->x_pm2_cnt_blk.addrh = 0x0;
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fadt->x_pm_tmr_blk.space_id = 1;
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fadt->x_pm_tmr_blk.bit_width = 32;
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fadt->x_pm_tmr_blk.bit_offset = 0;
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fadt->x_pm_tmr_blk.resv = 0;
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fadt->x_pm_tmr_blk.addrl = ACPI_PM_TMR_BLK;
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fadt->x_pm_tmr_blk.addrh = 0x0;
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fadt->x_gpe0_blk.space_id = 1;
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fadt->x_gpe0_blk.bit_width = 32;
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fadt->x_gpe0_blk.bit_offset = 0;
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fadt->x_gpe0_blk.resv = 0;
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fadt->x_gpe0_blk.addrl = ACPI_GPE0_BLK;
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fadt->x_gpe0_blk.addrh = 0x0;
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fadt->x_gpe1_blk.space_id = 1;
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fadt->x_gpe1_blk.bit_width = 0;
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fadt->x_gpe1_blk.bit_offset = 0;
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fadt->x_gpe1_blk.resv = 0;
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fadt->x_gpe1_blk.addrl = 0;
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fadt->x_gpe1_blk.addrh = 0x0;
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if (IS_ENABLED(CONFIG_CPU_AMD_MODEL_10XXX))
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amd_powernow_update_fadt(fadt);
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header->checksum = acpi_checksum((void *)fadt, sizeof(acpi_fadt_t));
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}
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