4bcc275d71
Change-Id: Ia473596e3c9a75587cd1288c8816bfef66bef82e Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59000 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
50 lines
1.3 KiB
C
50 lines
1.3 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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#include <bootmode.h>
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#include <boot/coreboot_tables.h>
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#include <device/device.h>
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#include <southbridge/intel/bd82x6x/pch.h>
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#include <southbridge/intel/common/gpio.h>
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#include <types.h>
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#include <vendorcode/google/chromeos/chromeos.h>
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#include "onboard.h"
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void fill_lb_gpios(struct lb_gpios *gpios)
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{
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struct lb_gpio chromeos_gpios[] = {
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/* Recovery: GPIO22 */
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{GPIO_REC_MODE, ACTIVE_LOW, !get_recovery_mode_switch(), "presence"},
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/* Hard code the lid switch GPIO to open. */
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{-1, ACTIVE_HIGH, 1, "lid"},
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/* Power Button */
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{-1, ACTIVE_HIGH, 0, "power"},
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/* Did we load the VGA option ROM? */
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{-1, ACTIVE_HIGH, gfx_get_init_done(), "oprom"},
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};
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lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios));
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}
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int get_recovery_mode_switch(void)
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{
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/* Recovery: GPIO22, active low */
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return !get_gpio(GPIO_REC_MODE);
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}
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int get_write_protect_state(void)
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{
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/* Write protect is active low, so invert it here */
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return !get_gpio(GPIO_SPI_WP);
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}
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static const struct cros_gpio cros_gpios[] = {
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CROS_GPIO_REC_AL(GPIO_REC_MODE, CROS_GPIO_DEVICE_NAME),
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CROS_GPIO_WP_AL(GPIO_SPI_WP, CROS_GPIO_DEVICE_NAME),
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};
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void mainboard_chromeos_acpi_generate(void)
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{
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chromeos_acpi_gpio_generate(cros_gpios, ARRAY_SIZE(cros_gpios));
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}
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