coreboot-kgpe-d16/src/mainboard/emulation/spike-riscv/Makefile.inc
Jonathan Neuschäfer 99f2f113ec riscv: Unify SBI call implementations under arch/riscv/
Note that currently, traps are only handled by the trap handler
installed in the bootblock. The romstage and ramstage don't override it.

TEST=Booted emulation/spike-qemu and lowrisc/nexys4ddr with a linux
     payload. It worked as much as before (Linux didn't boot, but it
     made some successful SBI calls)

Change-Id: Icce96ab3f41ae0f34bd86e30f9ff17c30317854e
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/17057
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2016-11-07 16:47:49 +01:00

25 lines
796 B
Makefile

##
## This file is part of the coreboot project.
##
## Copyright (C) 2013 Google Inc.
##
## This software is licensed under the terms of the GNU General Public
## License version 2, as published by the Free Software Foundation, and
## may be copied, distributed, and modified under those terms.
##
## This program is distributed in the hope that it will be useful,
## but WITHOUT ANY WARRANTY; without even the implied warranty of
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
## GNU General Public License for more details.
bootblock-y += uart.c
bootblock-y += rom_media.c
romstage-y += romstage.c
romstage-y += uart.c
romstage-y += rom_media.c
ramstage-y += uart.c
ramstage-y += rom_media.c
bootblock-y += memlayout.ld
romstage-y += memlayout.ld
ramstage-y += memlayout.ld