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Matt DeVillier 06abb91b22 device/i2c_bus: Check for self loop in bus link
When trying to find the parent i2c bus of a given device, ensure that
the bus link doesn't point to itself, else we'll get stuck in an
infinite loop.

Change-Id: I56cb6b2a3e4f98d2ce3ef2d8298e74d52661331c
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65229
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2022-06-21 12:28:07 +00:00
3rdparty Update vboot submodule to upstream main 2022-06-17 20:57:35 +00:00
Documentation Doc/soc/intel/mp_init: Mark up Reference section title as title 2022-06-20 12:01:41 +00:00
LICENSES
configs nb/intel/gm45: Enable 64bit support 2022-05-13 10:57:41 +00:00
payloads libpayload/Makefile.inc: Initialize vboot submodule 2022-06-20 13:54:31 +00:00
spd spd/lp5: Add SPD for Samsung K3LKCKC0BM-MGCP 2022-06-17 14:32:56 +00:00
src device/i2c_bus: Check for self loop in bus link 2022-06-21 12:28:07 +00:00
tests lib: Check for non-existent DIMMs in check_if_dimm_changed 2022-04-20 06:57:21 +00:00
util util/cbfstool: Set `USE_FLASHROM=0` to build vboot 2022-06-19 18:46:04 +00:00
.checkpatch.conf checkpatch.conf: Disable gerrit change ID for coreboot 2022-04-12 20:39:50 +00:00
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README.md

coreboot README

coreboot is a Free Software project aimed at replacing the proprietary BIOS (firmware) found in most computers. coreboot performs a little bit of hardware initialization and then executes additional boot logic, called a payload.

With the separation of hardware initialization and later boot logic, coreboot can scale from specialized applications that run directly firmware, run operating systems in flash, load custom bootloaders, or implement firmware standards, like PC BIOS services or UEFI. This allows for systems to only include the features necessary in the target application, reducing the amount of code and flash space required.

coreboot was formerly known as LinuxBIOS.

Payloads

After the basic initialization of the hardware has been performed, any desired "payload" can be started by coreboot.

See https://www.coreboot.org/Payloads for a list of supported payloads.

Supported Hardware

coreboot supports a wide range of chipsets, devices, and mainboards.

For details please consult:

Build Requirements

  • make
  • gcc / g++ Because Linux distribution compilers tend to use lots of patches. coreboot does lots of "unusual" things in its build system, some of which break due to those patches, sometimes by gcc aborting, sometimes - and that's worse - by generating broken object code. Two options: use our toolchain (eg. make crosstools-i386) or enable the ANY_TOOLCHAIN Kconfig option if you're feeling lucky (no support in this case).
  • iasl (for targets with ACPI support)
  • pkg-config
  • libssl-dev (openssl)

Optional:

  • gdb (for better debugging facilities on some targets)
  • ncurses (for make menuconfig and make nconfig)
  • flex and bison (for regenerating parsers)

Building coreboot

Please consult https://www.coreboot.org/Build_HOWTO for details.

Testing coreboot Without Modifying Your Hardware

If you want to test coreboot without any risks before you really decide to use it on your hardware, you can use the QEMU system emulator to run coreboot virtually in QEMU.

Please see https://www.coreboot.org/QEMU for details.

Website and Mailing List

Further details on the project, a FAQ, many HOWTOs, news, development guidelines and more can be found on the coreboot website:

https://www.coreboot.org

You can contact us directly on the coreboot mailing list:

https://www.coreboot.org/Mailinglist

The copyright on coreboot is owned by quite a large number of individual developers and companies. Please check the individual source files for details.

coreboot is licensed under the terms of the GNU General Public License (GPL). Some files are licensed under the "GPL (version 2, or any later version)", and some files are licensed under the "GPL, version 2". For some parts, which were derived from other projects, other (GPL-compatible) licenses may apply. Please check the individual source files for details.

This makes the resulting coreboot images licensed under the GPL, version 2.