028cba9266
This patch adds code to initialize the two DWC3 USB host controllers and their associated PHYs to the IPQ806x SoC (closely imitating the existing DWC3 implementation for Exynos5), and uses them to initialize USB on the Storm mainboard. BUG=chrome-os-partner:29375 TEST=Hack up netboot to get around missing SPI flash, load a file over TFTP. Hack a storage read into the storage attach function, dump the data and confirm that it looks right. Enable USB debugging and confirm 3.0 devices get enumerated at SuperSpeed (mostly). Original-Change-Id: Iaf7b96bef994081ca222b7de9d8e8c49751d3f1d Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/202157 Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> (cherry picked from commit 6349e7281d5accb1247acb0537a48fa3a5e1bf97) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I749d265d45c6a807a7559bd4df2490a6eb8067af Reviewed-on: http://review.coreboot.org/8056 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
66 lines
2 KiB
Makefile
66 lines
2 KiB
Makefile
##
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## This file is part of the coreboot project.
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##
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## Copyright 2014 Google Inc.
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##
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## This program is free software; you can redistribute it and/or modify
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## it under the terms of the GNU General Public License as published by
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## the Free Software Foundation; version 2 of the License.
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##
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## This program is distributed in the hope that it will be useful,
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## but WITHOUT ANY WARRANTY; without even the implied warranty of
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## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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## GNU General Public License for more details.
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##
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## You should have received a copy of the GNU General Public License
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## along with this program; if not, write to the Free Software
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## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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##
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bootblock-y += bootblock.c
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bootblock-y += clock.c
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bootblock-y += gpio.c
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bootblock-$(CONFIG_SPI_FLASH) += spi.c
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bootblock-y += timer.c
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bootblock-$(CONFIG_DRIVERS_UART) += uart.c
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romstage-y += clock.c
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romstage-y += gpio.c
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romstage-$(CONFIG_SPI_FLASH) += spi.c
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romstage-y += timer.c
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romstage-$(CONFIG_DRIVERS_UART) += uart.c
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romstage-y += cbmem.c
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ramstage-y += cbmem.c
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ramstage-y += clock.c
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ramstage-y += gpio.c
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ramstage-y += soc.c
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ramstage-$(CONFIG_SPI_FLASH) += spi.c
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ramstage-y += timer.c
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ramstage-$(CONFIG_DRIVERS_UART) += uart.c
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ramstage-y += usb.c
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ifeq ($(CONFIG_USE_BLOBS),y)
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# Generate the actual coreboot bootblock code
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$(objcbfs)/bootblock.raw: $(objcbfs)/bootblock.elf
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@printf " OBJCOPY $(subst $(obj)/,,$(@))\n"
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$(OBJCOPY_bootblock) -O binary $< $@.tmp
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@mv $@.tmp $@
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# Add MBN header to allow SBL3 to start coreboot bootblock
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$(objcbfs)/bootblock.mbn: $(objcbfs)/bootblock.raw
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@printf " ADD MBN $(subst $(obj)/,,$(@))\n"
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./util/ipqheader/ipqheader.py $(CONFIG_BOOTBLOCK_BASE) $< $@.tmp
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@mv $@.tmp $@
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# Create a complete bootblock which will start up the system
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$(objcbfs)/bootblock.bin: $(call strip_quotes,$(CONFIG_SBL_BLOB)) \
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$(objcbfs)/bootblock.mbn
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@printf " CAT $(subst $(obj)/,,$(@))\n"
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@cat $^ > $@.tmp
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@mv $@.tmp $@
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endif
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CPPFLAGS_common += -Isrc/soc/qualcomm/ipq806x/include
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