Felix Held 0728c46925 soc/amd/cezanne: add pci_devs.h ... Change-Id: I9e3ee4c98a85068dc87ef96aaf65a09c6df1572d Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49781 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>		2021-01-22 19:30:13 +00:00
..
include/soc	soc/amd/cezanne: add pci_devs.h	2021-01-22 19:30:13 +00:00
aoac.c	soc/amd/cezanne: add AOAC support	2021-01-14 15:42:34 +00:00
bootblock.c	soc/amd/cezanne: add caching setup in bootblock	2020-12-13 22:18:03 +00:00
chip.c	soc/amd/cezanne: add config.c and minimal chip.h	2020-12-06 19:05:47 +00:00
chip.h	soc/amd/cezanne: add config.c and minimal chip.h	2020-12-06 19:05:47 +00:00
chipset.cb	soc/amd/cezzane: Add a minimal chipset tree	2021-01-11 07:42:12 +00:00
config.c	soc/amd/cezanne: add config.c and minimal chip.h	2020-12-06 19:05:47 +00:00
early_fch.c	soc/amd/cezanne: add AOAC support	2021-01-14 15:42:34 +00:00
gpio.c	soc/amd/cezanne: add GPIO support	2020-12-18 17:20:56 +00:00
Kconfig	soc/amd/cezanne: include LAPIC code and set MAX_CPUS to 16	2021-01-21 22:26:40 +00:00
Makefile.inc	soc/amd/cezanne: include LAPIC code and set MAX_CPUS to 16	2021-01-21 22:26:40 +00:00
reset.c	soc/amd/cezanne: add 0xcf9 reset	2020-12-11 17:44:42 +00:00
romstage.c
uart.c	soc/amd/cezanne,picasso/uart: remove unneeded struct name	2021-01-15 01:19:59 +00:00