a73b93157f
It encourages users from writing to the FSF without giving an address. Linux also prefers to drop that and their checkpatch.pl (that we imported) looks out for that. This is the result of util/scripts/no-fsf-addresses.sh with no further editing. Change-Id: Ie96faea295fe001911d77dbc51e9a6789558fbd6 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/11888 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
144 lines
No EOL
3.4 KiB
C
144 lines
No EOL
3.4 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2015 Timothy Pearson <tpearson@raptorengineeringinc.com>, Raptor Engineering
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* Copyright (C) 2012 Advanced Micro Devices, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <stdint.h>
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#include <stdlib.h>
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#include <string.h>
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#include <arch/io.h>
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#include <console/console.h>
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#include <spi-generic.h>
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#include <spi_flash.h>
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#include <device/device.h>
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#include <device/pci.h>
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#include <device/pci_ops.h>
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#define AMD_SB_SPI_TX_LEN 8
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static uint32_t get_spi_bar(void)
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{
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device_t dev;
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dev = dev_find_slot(0, PCI_DEVFN(0x14, 3));
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return pci_read_config32(dev, 0xa0) & ~0x1f;
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}
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void spi_init(void)
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{
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/* Not needed */
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}
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unsigned int spi_crop_chunk(unsigned int cmd_len, unsigned int buf_len)
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{
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return min(AMD_SB_SPI_TX_LEN - cmd_len, buf_len);
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}
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static void reset_internal_fifo_pointer(void)
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{
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uint32_t spibar = get_spi_bar();
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do {
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write8((void *)(spibar + 2),
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read8((void *)(spibar + 2)) | 0x10);
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} while (read8((void *)(spibar + 0xd)) & 0x7);
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}
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static void execute_command(void)
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{
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uint32_t spibar = get_spi_bar();
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write8((void *)(spibar + 2), read8((void *)(spibar + 2)) | 1);
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while ((read8((void *)(spibar + 2)) & 1) &&
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(read8((void *)(spibar+3)) & 0x80));
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}
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int spi_claim_bus(struct spi_slave *slave)
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{
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/* Handled internally by the SB700 */
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return 0;
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}
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void spi_release_bus(struct spi_slave *slave)
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{
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/* Handled internally by the SB700 */
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}
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struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs)
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{
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struct spi_slave *slave = malloc(sizeof(*slave));
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if (!slave) {
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return NULL;
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}
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memset(slave, 0, sizeof(*slave));
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return slave;
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}
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int spi_xfer(struct spi_slave *slave, const void *dout,
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unsigned int bytesout, void *din, unsigned int bytesin)
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{
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/* First byte is cmd which cannot be sent through the FIFO. */
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u8 cmd = *(u8 *)dout++;
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u8 readoffby1;
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u8 readwrite;
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u8 count;
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uint32_t spibar = get_spi_bar();
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bytesout--;
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/*
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* Check if this is a write command attempting to transfer more bytes
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* than the controller can handle. Iterations for writes are not
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* supported here because each SPI write command needs to be preceded
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* and followed by other SPI commands, and this sequence is controlled
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* by the SPI chip driver.
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*/
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if (bytesout > AMD_SB_SPI_TX_LEN) {
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printk(BIOS_DEBUG, "FCH SPI: Too much to write. Does your SPI chip driver use"
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" spi_crop_chunk()?\n");
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return -1;
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}
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readoffby1 = bytesout ? 0 : 1;
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readwrite = (bytesin + readoffby1) << 4 | bytesout;
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write8((void *)(spibar + 1), readwrite);
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write8((void *)(spibar + 0), cmd);
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reset_internal_fifo_pointer();
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for (count = 0; count < bytesout; count++, dout++) {
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write8((void *)(spibar + 0x0C), *(u8 *)dout);
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}
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reset_internal_fifo_pointer();
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execute_command();
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reset_internal_fifo_pointer();
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/* Skip the bytes we sent. */
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for (count = 0; count < bytesout; count++) {
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cmd = read8((void *)(spibar + 0x0C));
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}
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reset_internal_fifo_pointer();
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for (count = 0; count < bytesin; count++, din++) {
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*(u8 *)din = read8((void *)(spibar + 0x0C));
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}
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return 0;
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} |