90989b3210
Initial mainboard code MSI PRO Z690-A DDR4 WIFI. The platform boots up up to romstage where it returns from FSP memory init with an error. What works: - open-source CAR setup - NCT6687D serial port with TX pin exposed on JBD1 header - SMBus reading SPD from all 4 DIMMs This board will serve as a reference board for enabling Alder Lake-S support in coreboot. More code and functionalities will be added in subsequent patches as src/soc/alderlake code will be improved for PCH-S. TEST=Extract the microcode from vendor firmware and include it in the build. The platform should print the console on the serial port even without FSP blob. Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: I5df69822dbb3ff79e087408a0693de37df2142e8 Signed-off-by: Igor Bagnucki <igor.bagnucki@3mdeb.com> Signed-off-by: Michał Kopeć <michal.kopec@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63463 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com>
16 lines
563 B
Text
16 lines
563 B
Text
CONFIG_VENDOR_MSI=y
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CONFIG_CBFS_SIZE=0x1000000
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CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000
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CONFIG_TIANOCORE_BOOT_TIMEOUT=3
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CONFIG_BOARD_MSI_Z690_A_PRO_WIFI_DDR4=y
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# CONFIG_SMMSTORE is not set
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CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0=y
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CONFIG_POST_DEVICE_PCI_PCIE=y
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CONFIG_POST_IO_PORT=0x80
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CONFIG_PAYLOAD_TIANOCORE=y
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CONFIG_TIANOCORE_REPOSITORY="https://github.com/Dasharo/edk2.git"
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CONFIG_TIANOCORE_TAG_OR_REV="origin/dasharo"
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CONFIG_TIANOCORE_CBMEM_LOGGING=y
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CONFIG_TIANOCORE_FOLLOW_BGRT_SPEC=y
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CONFIG_TIANOCORE_SD_MMC_TIMEOUT=1000
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CONFIG_POWER_STATE_OFF_AFTER_FAILURE=y
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