Lijian Zhao 031020e431 soc/intel/cannonlake: Correct PMC/GPIO routing information ... PMC and GPIO DWx definition is not identical, hence update that to correct information. For cannonlake lp PCH, GPIO group C, group E and group GPD is different for PMC GPIO_CFG and GPIO MISCCFG. Also add function call to set up GPE routing in bootblock stage. TEST=Boot up into OS, and manually check PMC GPE status Change-Id: I1edb83edabc72e8a762b129cf51dcd936cd37ddf Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/22908 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>		2018-01-05 20:44:15 +00:00
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amd	soc/amd/common: load post-memory AGESA as rmodule	2018-01-05 01:16:50 +00:00
broadcom	soc: Add Kconfig for each soc vendor	2017-10-23 17:18:32 +00:00
dmp	soc: Add Kconfig for each soc vendor	2017-10-23 17:18:32 +00:00
imgtec	soc: Add Kconfig for each soc vendor	2017-10-23 17:18:32 +00:00
intel	soc/intel/cannonlake: Correct PMC/GPIO routing information	2018-01-05 20:44:15 +00:00
lowrisc	RISC-V boards: Stop using the config string	2017-11-07 12:31:00 +00:00
marvell	soc: Add Kconfig for each soc vendor	2017-10-23 17:18:32 +00:00
mediatek	soc/mediatek/mt8173: Remove cast of `NULL*` to `void *`	2017-11-03 16:03:30 +00:00
nvidia	soc: Add Kconfig for each soc vendor	2017-10-23 17:18:32 +00:00
qualcomm	soc: Add Kconfig for each soc vendor	2017-10-23 17:18:32 +00:00
rockchip	google/gru: Stop mucking with unused I2S0 pins in codec config	2017-12-11 19:03:45 +00:00
samsung	soc: Add Kconfig for each soc vendor	2017-10-23 17:18:32 +00:00
ucb	riscv: Remove config string support	2017-12-02 05:25:00 +00:00